Abstract
Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 µW for 6T SRAM cell, 0.456/0.752 ns, 1.09 µW for 7T SRAM cell, 0.517/0.392 ns, 1.82 µW for 8T SRAM cell, 0.388/0.181 ns, 1.3 µW for 9T SRAM cell and 0.167/0.242 ns, 2.01 µW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Rabaey, J.M., Chandrakasan, A.P., Nikolic, B.: Digital Integrated Circuits: A Design Perspective. PHI Learning, 2nd edn. ISBN-10: 8120322576 (2003)
Calhoun, B.H., Chandrakasan, A.P.: Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE J. Solid State Circuits 41(7), 1673–1679 (2006)
Ramy, E.A., Bayoumi, M.A.: Low-power cache design using 7T SRAM cell. IEEE Trans. Circuits Syst.-II. Express Briefs 54(4), 318–322 (2007)
Kumar, V., Khanna, G.: A novel 7T SRAM cell design for reducing leakage power and improved stability. In: International Conference on Advanced Communication Control and Computing Technologies (ICACCCT-2014), pp. 56–59. Ramanathapuram (2014)
Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.: Stable SRAM cell design for the 32 nm node and beyond. In: Symposium VLSI Technical Digest, pp. 292–293 (2005)
Moradi, F., Madsen, J.K.: Improved read and write margins using a novel 8T-SRAM cell. In: 22nd International Conference on Very Large Scale Integration (VLSI-SoC-2014), pp. 1–5 (2014)
Pasandi, G., Fakhraie, A.: 256-kb 9T near-threshold SRAM with 1 k cells per bit line and enhanced write and read operations. IEEE Trans. VLSI Syst. (2015)
Liu, Z., Kursun, V.: Characterization of a novel nine-transistor SRAM cell. IEEE Trans. VLSI Syst. 16(4), 488–492 (2008)
Calhoun, B.H., Chandrakasan, A.P.: A 256 kb subthreshold SRAM in 65 nm CMOS. In: Solid State Circuits Conference (ISSCC-2006), session 34, pp. 2592–2601 (2006)
Islam, A., Hasan, M.: Leakage characterization of 10T SRAM cell. IEEE Trans. Electron Dev 59(3), 631–638 (2012)
Khare, K., Khare, N., Kulhade, N., Deshpande, P.: VLSI design and analysis of low power 6T SRAM cell using cadence tool. Semiconductor electronics, IEEE international conference (ICSE-2008), pp. 117–121. (2008)
Akashe, S., Tiwari, N., Sharma, R.: Simulation and stability analysis of 6T and 9T SRAM cell in 45 nm. In: 2nd International Conference on Power, Control and Embedded Systems (ICPCES-2012), pp 1–6 (2012)
Chopade, S., Padole, D.: Stability analysis of 6T SRAM cell for nanoscale FD-SOI technology. In: Annual IEEE India Conference (INDICON-2014), pp. 1–6 (2014)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Appendix: Steps to Calculate SNM and MATLAB Code to Plot the Butterfly Curve
Appendix: Steps to Calculate SNM and MATLAB Code to Plot the Butterfly Curve
To calculate SNM the basic 6T SRAM cell and the process followed has been shown in Figs. 16 and 17 respectively. Below MATLAB code is given for it.
[a,T,aT] = xlsread(‘inverterA.xlsx’)
t = a(:,1);y = a(:,2); plot(y,t,’red’)
hold on
[b,bT,bT] = xlsread(‘inverterB.xlsx’)
s = b(:,1);r = b(:,2)
axis square; plot(s,r,’red’)
Rights and permissions
Copyright information
© 2016 Springer Science+Business Media Singapore
About this paper
Cite this paper
Joshi, V.K., Lobo, H.C. (2016). Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology. In: Choudhary, R., Mandal, J., Auluck, N., Nagarajaram, H. (eds) Advanced Computing and Communication Technologies. Advances in Intelligent Systems and Computing, vol 452. Springer, Singapore. https://doi.org/10.1007/978-981-10-1023-1_3
Download citation
DOI: https://doi.org/10.1007/978-981-10-1023-1_3
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-1021-7
Online ISBN: 978-981-10-1023-1
eBook Packages: EngineeringEngineering (R0)