Abstract
Background: The rapid advancement of multimedia technology has made the data communication and data sharing so comfortable through wireless network and Internet. During this multimedia communication, the piracy of the multimedia content is a primary concern (i.e. anyone can duplicate or alter the originality). One of the most efficient techniques to protect the multimedia data is watermarking. It is the process of adding a secret digital signature to the host content in a visible or invisible form. The process of watermarking will be of reversible or irreversible nature. Method: In this paper, a reversible watermarking strategy using prediction technique with its hardware architecture is proposed. In the VLSI implementation aspect three different architectural structures are proposed as pipelined, parallel and dataflow architecture with embedding concept. Findings: Finally, all the three architectural designs are modelled and implemented using Verilog HDL. The entire process is integrated in a specific chip. Application: It can be used as a separate co-processor for carrying out the watermarking in real time with any multimedia devices.
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References
Cox IJ et al (2008) Digital watermarking and steganography. Morgan Kaufmann Publishers, USA
Johnson NF, Jajodia S (1998) Exploring steganography: seeing the unseen. Comput Pract 31(2):26–34
Kutter M, Petitcolas FAP (1999) A fair benchmark for image watermarking systems. In Electronic imaging ‘99. Security and watermarking of multimedia contents, vol 3657, Sans Jose, CA, USA
Petitcolas FAP, Anderson RJ, Kuhn MG (1999) Information hiding—a Survey. Proc of the IEEE, Spec Issue on Prot of Multimedia Content 87(7):1062–1078
Anderson RJ, Petitcolas FAP (1998) On the limits of steganography. IEEE J Sel Areas Commun 16:474–481
Hosinge CW, Jones PW, Rabbani M, Stoffel JC (2001) Lossless recovery of an original image containing embedded data. U.S. patent 6 278791
Kamstra LHJ, Heijmans AM (2005) Reversible data embedding into images using wavelet techniques and sorting. IEEE Trans Image Process 14(12):2082–2090
Tian J (2002) Reversible watermarking by difference expansion. In: Proc. workshop on multimedia and security. In: Fridrich DJ, Wohlmacher P (eds) Dec 2002, pp 19–22
Alattar AM (2004) Reversible watermark using the difference expansion of a generalized integer transform. IEEE Trans Image Process 19(8):1147–1156
Alattar M (2003) Reversible watermark using difference expansion of triplets. In: Proceedings of the international conference image process, vol 1. Barcelona, Spain, 2003, pp 501–504
Alattar M (2004) Reversible watermark using difference expansion of quads. In: Proc. IEEE Int. Conf. acoustics, speech, signal process, vol 3. Toulouse, France, 2004, pp 377–380
Sachnev V, Kim HJ, Nam J, Suresh S, Shi YQ (2009) Reversible watermarking algorithm using sorting and prediction. IEEE Trans Circ Syst Video Technol 19(7):989–999
Raveendra SR, Sakthivel SM (2015) A FPGA implementation of dual images based reversible data hiding technique using LSB matching with pipelining. Indian J Sci Technol 8(25)
Sakthivel SM, Sankar RA (2015) A real time watermarking of grayscale images without altering it’s content. In: Proceedings of the international conference on VLSI systems, architecture, technology and applications, Bangalore, India, 8–10 Jan 2015
Sakthivel SM, Sankar RA (2015) FPGA implementation of data hididng in grayscale images using neighbour mean interpolation. In: Proceedings of the international conference on electronics and communication systems (ICECS), Feb 2015, pp 1124–1127
Sakthivel SM, Sankar RA (2015) A VLSI architecture for watermarking of grayscale images using weighted median prediction. In: Proceedings of the international conference on electronics and communication systems (ICECS), Feb 2015, pp 1128–1131
Reddy SR, Sakthivel SM (2015) A FPGA implementation of data hiding using LSB matching method. Int J Res Eng Technol 4(3)
Mohanty SP, Ranganathan N, Namballa RK (2004) VLSI implementation of visible watermarking for a secure digital still camera design. In: IEEE proceedings of the 17th I Conference VLSI design (VLSID’04)
Mohanty SP, Ranganathan N, Balakrishnan K (2006) A dual voltage frequency VLSI chip for image watermarking in DCT domain. IEEE Trans Circuits Syst II (TCAS-II) 53(5):394–398
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Murali, M., Ravi Sankar, A., Sakthivel, S.M. (2018). Pipelined and Parallel Architecture of Reversible Watermarking for Greyscale Images. In: Li, J., Sankar, A., Beulet, P. (eds) VLSI Design: Circuits, Systems and Applications . Lecture Notes in Electrical Engineering, vol 469. Springer, Singapore. https://doi.org/10.1007/978-981-10-7251-2_25
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DOI: https://doi.org/10.1007/978-981-10-7251-2_25
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