Abstract
In recent years, ultra low voltage (ULV) operation is gaining more importance to achieve minimum energy consumption. In this paper, the performance of the gate level body biasing (GLBB) is evaluated in subject to the subthreshold hybrid full adder logic design which employs CMOS logic and Transmission Gate (TG) logic. The performance metrics—energy, power, area, delay, and EDP are calculated and compared with the conventional CMOS (C-CMOS) Full adder. The simulations are performed in cadence at ULV of 200 mV using 90 nm CMOS technology. The obtained results showed that the proposed subthreshold hybrid full adder circuit with GLBB scheme achieves more than 44% savings in delay, 20% savings in energy consumption, and 55% savings in EDP in comparison with the conventional CMOS configuration and other hybrid counterparts.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Alice Wang, B.H. Calhoun, and A. Chandrakasan. Subthreshold design for ultra low-power systems. 1st edition. Springer: 2006.
H. Soeleman and K. Roy. Ultra low power Subthreshold digital logic circuits. Proceedings of IEEE conference on Low power electronics and design, 1999, 94–96.
Neil. H. Weste and David Harris. CMOS VLSI design-A circuits and systems perspective. 3rdEdition. Addison Wesley: 2004.
Zimmermann R, Fichtner W. Low-power logic styles: CMOS versus pass-transistor logic. IEEE Journal of Solid-State Circuits, 1997, 32(7):1079–1090.
Alioto M, Cataldo GD, Palumbo G. Mixed full adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal, 2007, 38(1):130–139.
Shams AM, Darwish TK, Bayoumi MA. Performance analysis of low-power 1-bit cmos full adder cells. IEEE Transactions on VLSI Systems, 2002, 10(1):20–29.
M. Lanuzza, R. Taco and D. Albano, Dynamic gate-level body biasing for subthreshold digital design, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, Santiago, 2014, pp. 1–4.
Partha B, Bijoy K, Sovan G and Vinay K. Performance Analysis of a Low-Power High Speed Hybrid 1-bit Full Adder Circuit. IEEE Transactions on VLSI Systems, 2015, 23(10): 2001–2008.
R. Taco, M. Lanuzza, and D. Albano, “Ultra-Low-Voltage Self Body Biasing Scheme and its application to basic Arithmetic Circuits”. J. VLSI Design, 2015, pp. 1–10.
Assaderaghi F, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation. IEDM Tech. Dig., 1994, pp. 809–812.
Shih-Fen Huang et.al, Scalability and biasing strategy for CMOS with active well bias. 2001 Symposium on VLSI Technology, pp. 107–108.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Sanapala, K., Shree, L.R., Sakthivel, R. (2018). Design of Ultralow Voltage-Hybrid Full Adder Circuit Using GLBB Scheme for Energy-Efficient Arithmetic Applications. In: Anguera, J., Satapathy, S., Bhateja, V., Sunitha, K. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 471. Springer, Singapore. https://doi.org/10.1007/978-981-10-7329-8_22
Download citation
DOI: https://doi.org/10.1007/978-981-10-7329-8_22
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-7328-1
Online ISBN: 978-981-10-7329-8
eBook Packages: EngineeringEngineering (R0)