Abstract
The most critical constraints in System on chip (SoC’s), to determine the performance are area and power. As technology scales down, innovative clock tree design techniques are required to improve the skew. Hence, skew minimization design should be introduced in VLSI physical design at early stages of SoC’s where it has the highest benefits for QoR. In this paper, skew balance methodology using H-Tree is introduced in Multisource CTS design.
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We would like to thank Intel technology Pvt Ltd. for their support and encouragement.
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Bhat, V.K., Surendra, H.H., Archana, H.R. (2020). Skew Analysis on Multisource Clock Tree Synthesis Using H-Tree Structure. In: Kalya, S., Kulkarni, M., Shivaprakasha, K. (eds) Advances in Communication, Signal Processing, VLSI, and Embedded Systems. Lecture Notes in Electrical Engineering, vol 614. Springer, Singapore. https://doi.org/10.1007/978-981-15-0626-0_26
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DOI: https://doi.org/10.1007/978-981-15-0626-0_26
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