Abstract
Crypto core finds implementaions in software, Application Specific Integrated Circuit (ASIC), and Field Programmable Gate Array (FPGA). The crypto software programs achieve very less throughput, whereas ASIC implementations serve reasonably cost-effective design with efficient performance. In ASIC platform, once the design is implemented, it is not possible to alter those circuit connection, whereas FPGA is a flexible solution which can be reconfigured in the field. For huge number of gate applications, FPGA is cost-effective compared to ASIC and software implementation. This submission explores FPGA design spaces of Grain crypto hardware core. The article implements seven loop unrolled architectures which are implemented in Xilinx Zynq FPGA using VHDL language in Vivado Design Suit. The results show that three basic systems’ parameters such as resource usage, power consumption, and throughput of proposed implementation are satisfactorily optimized compared to existing literature.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Aumasson, J.-P., Dinur, I., Henzen, L., Meier, W., Shamir, A.: Efficient FPGA implementations of high-dimensional cube testers on the stream cipher grain-128. IACR Cryptology ePrint Arch. 2009, 218 (2009)
Liberatori, M., Otero, F., Bonadero, J.C., Castineira, J.: AES-128 cipher. high speed, low cost fpga implementation. In: 2007 3rd Southern Conference on Programmable Logic, 2007. SPL ’07, pp. 195–198, Feb 2007
Paul, R., Dey, H., Chakrabarti, A., Ghosh, R.: Accelerating more secure RC4 : implementation of seven FPGA designs in stages upto 8 byte per clock (2016). CoRR, arXiv:1609.01389
Hell, M., Johansson, T., Meier, W.: Grain: a stream cipher for constrained environments. IJWMC 2(1), 86–93 (2007)
Sahu, S.K.: FPGA implementation of RSA encryption system. J. Comput. Appl. 19(9), 10–12 (2011)
Paul, R., Saha, S., Zaman, J.K.M.S.U., Das, S., Chakrabarti, A., Ghosh, R.: A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication (2012). CoRR, arXiv:1205.1737
In: NSA Approved Defense-Grade Spartan\({\textregistered }\)-6Q FPGA in Production for Highest Level Cryptographic Capabilities Strengthens Xilinx Secure Leadership. Xilinx, Inc. website, pp. 138 –148, 31 Aug 2011
Sau, S., Paul, R., Biswas, T., Chakrabarti, A.: A novel AES-256 implementation on FPGA using co-processor based architecture. In: Proceedings of the International Conference on Advances in Computing, Communications and Informatics, ICACCI ’12, New York, NY, USA, pp. 632–638. ACM (2012)
Paul, R., Chakrabarti, A., Ghosh, R.: Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm. Microprocess. Microsyst. 40(C), 124–136 (2016)
Paul, R., Saha, S., Pal, C., Sau, S.: Novel architecture of modular exponent on reconfigurable system. In: 2012 Students Conference on Engineering and Systems (SCES), pp. 1–6, Mar 2012
Microblaze Xilinx: Microblaze processor reference guide. Xilinx, Microblaze. http://www.xilinx.com/tools/microblaze.htm
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Baidya, P., Paul, R., Sau, S. (2020). High-Speed Loop Unrolled Grain Architecture in Reconfigurable Hardware. In: Pati, B., Panigrahi, C., Buyya, R., Li, KC. (eds) Advanced Computing and Intelligent Engineering. Advances in Intelligent Systems and Computing, vol 1089. Springer, Singapore. https://doi.org/10.1007/978-981-15-1483-8_15
Download citation
DOI: https://doi.org/10.1007/978-981-15-1483-8_15
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-1482-1
Online ISBN: 978-981-15-1483-8
eBook Packages: EngineeringEngineering (R0)