Abstract
The power consumption and speed of a device is a crucial factor as most of the designs move towards the system-in-package and system-on-chip products. As the size of the device scale down, speed and power consumption doesn’t go hand in hand. Switching power in a CMOS circuit is a prime component of the total power consumption. This switching power is caused by simultaneous charging and discharging of the load capacitances when the signal undergoes transition. The speed of a digital circuit is determined by how fast the circuit can generate outputs from the given inputs. There are various ways to reduce power consumption such as voltage scaling, clock gating, reversible logic, and so on. For increasing the speed of a circuit, delay inside the logic should be reduced. The choice of a smarter design architecture helps in improving the circuit speed. This work focuses on an ALU design using Vedic algorithm and reversible logic. It aims for better speed and power. The proposed Vedic algorithm based ALU design yields 6.7% decrease in dynamic power and 2.2% decrease in a number of cells used.
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Jadhav K, Vibhute A, Iyer S, Dhanabal R (2015) Novel vedic mathematics based ALU using application specific reversibility. In: 2015 IEEE 9th international conference on intelligent systems and control (ISCO), pp 1–5. IEEE
Morrison M, Ranganathan N (2011) Design of a reversible ALU based on novel programmable reversible logic gate structures. In: 2011 IEEE computer society annual symposium on VLSI (ISVLSI), pp 126–131. IEEE
Nagamani A, Jayashree H, Bhagyalakshmi H (2011) Novel low power comparator design using reversible logic gates. Indian J Comput Sci Eng (IJCSE) 2(4):566–574
Patil HP, Sawant S (2015) FPGA Implementation of conventional and vedic algorithm for energy efficient multiplier. In: 2015 International conference on energy systems and applications, pp 583–587. IEEE
Gokul PR, Prabhu E, Mangalam H (2014) Performance comparison of multipliers based on square and multiply and Montgomery algorithms. In: International conference on green computing, communication and electrical engineering (ICGCCEE), pp 1–5
Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5(3):183–191
Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17(6):525–532
Balakumaran R, Prabhu E (2016) Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder. In: International conference on circuit, power and computing technologies (ICCPCT), pp 1–7. IEEE
Haritha H, Ramesh SR (2017) Design of an enhanced array based approximate arithmetic computing model for multipliers and squarers. In: 2017 14th IEEE India council international conference (INDICON), pp 1–5. IEEE
Rakshith T, Saligram R (2013) Design of high speed low power multiplier using reversible logic: a vedic mathematical approach. In: International conference on circuits, power and computing technologies (ICCPCT), pp 775–781. IEEE
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Lachireddy, D., Ramesh, S.R. (2020). Power and Delay Efficient ALU Using Vedic Multiplier. In: Sengodan, T., Murugappan, M., Misra, S. (eds) Advances in Electrical and Computer Technologies. Lecture Notes in Electrical Engineering, vol 672. Springer, Singapore. https://doi.org/10.1007/978-981-15-5558-9_61
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DOI: https://doi.org/10.1007/978-981-15-5558-9_61
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