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Qualitative and Quantitative Analysis of Parallel-Prefix Adders

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Advances in VLSI and Embedded Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 676))

Abstract

Binary adders are one of the most recurrent architectures in digital VLSI design, and the choice of adder architecture can boost or bust the overall performance of the design. Parallel-Prefix Adders are preferred over conventional adders for higher wordlengths. In this paper, a comprehensive, qualitative and quantitative analysis of popular Parallel-Prefix Adders for various wordlengths (N = 4, 8, 16 and 32) is presented. The adders are implemented using VHDL coding and Vivado 2016.2 HLx platform targeted for Basys3 board and compared on the basis of Device Utilization, Speed and Power Consumption. Results indicate that Kogge–Stone adder is the fastest adder with \(F_{max}\) = 104.93 MHz but is most area-power inefficient consuming 133 LUTs and 23.756 W power at 10 GHz. Sklansky adder is most power efficient consuming 22.857 W power at 10 GHz. Brent–Kung adder is area optimum consuming 62 LUTs.

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Acknowledgements

The authors express their gratitude to Special Manpower Development Program for Chips to System Design (SMDP-C2SD) project under Ministry of Electronics and Information Technology, Government of India, for providing access to tools required to conduct this research work.

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Authors and Affiliations

  1. Electronics Engineering Department, Sardar Vallabhbhai National Institute of Technology, Surat, India

    Sudhanshu Janwadkar & Rasika Dhavse

Authors
  1. Sudhanshu Janwadkar
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  2. Rasika Dhavse
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Corresponding author

Correspondence to Sudhanshu Janwadkar .

Editor information

Editors and Affiliations

  1. Department of Electronics Engineering, S. V. National Institute of Technology, Surat, Gujarat, India

    Zuber Patel

  2. Department of Electronics Engineering, S. V. National Institute of Technology, Surat, Gujarat, India

    Shilpi Gupta

  3. National Institute of Technology Goa, Ponda, Goa, India

    Nithin Kumar Y. B.

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Janwadkar, S., Dhavse, R. (2021). Qualitative and Quantitative Analysis of Parallel-Prefix Adders. In: Patel, Z., Gupta, S., Kumar Y. B., N. (eds) Advances in VLSI and Embedded Systems. Lecture Notes in Electrical Engineering, vol 676. Springer, Singapore. https://doi.org/10.1007/978-981-15-6229-7_6

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  • DOI: https://doi.org/10.1007/978-981-15-6229-7_6

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-6228-0

  • Online ISBN: 978-981-15-6229-7

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