Minimization of Drain-End Leakage of a U-Shaped Gated Tunnel FET for Low Standby Power (LSTP) Application

Abstract

In this paper, for the first time, the transfer characteristic of a ‘U’-shaped gated tunnel FET (TFET) has been thoroughly investigated considering the real-time adverse effects of gate-to-drain direct tunneling current and gate-induced drain leakage (GIDL) effect using SILVACO ATLAS device simulator. Clearly, these leakage phenomena degrade the device performance, especially for low standby power (LSTP) operation. Hence, for the first time, a novel design modification has been proposed in terms of the optimization of the oxide thickness (T_GD) of right vertical arm of the U-shaped gate, in order to mitigate the aforementioned problem. It has been found that when the T_GD value is increased to 7 nm from the equivalent oxide thickness (EOT) value of 1.6 nm, the ultimate device becomes optimized in terms of the performance matrices like, I_OFF, SS_min, I_ON/I_OFF, etc. Moreover, 43% reduction in delay and almost 11 decades of OFF-state power reduction have been obtained for the optimized device than that of the device having T_GD = 1.6 nm, for gate length of 70 nm.