Abstract
An energy and area efficient switching scheme for a 4-bit charge redistribution switch capacitor (SC) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. It is based on conventional binary search algorithm. The charge redistribution type architecture implemented in the proposed scheme is fully differential in nature, hence the operation of the two sides is complementary. The proposed switching technique consumes zero energy in the first and third comparison cycles. It It is seen that the switching energy saving is as high as 99%. The method thus becomes one of the most energy efficient switching schemes recently presented by different researchers. Besides such an enormous savings in energy, it also achieves a 75% reduction in unit capacitance requirements over the conventional method. The common mode voltage variations at the comparator inputs have been studied and it is seen that the same is better than either the modified merged or hybrid method.
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Ghoshal, P., Dey, C., Sen, S.K. (2021). A Low Energy and Area Efficient Switching Scheme for a Charge Redistribution SAR ADC Architecture. In: Banerjee, S., Mandal, J.K. (eds) Advances in Smart Communication Technology and Information Processing. Lecture Notes in Networks and Systems, vol 165. Springer, Singapore. https://doi.org/10.1007/978-981-15-9433-5_35
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DOI: https://doi.org/10.1007/978-981-15-9433-5_35
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