Abstract
Prompt escalation of technology in the realm of electronics is beyond comparison. Pronounced digital circuits like registers, buffers, counters and sequential state machines make large scale utilization of Delay Flipflop (D flipflop). Subsequently, this work propounds several design facets of a D flipflop. Consequently, a CMOS based conventional NAND circuit is considered and examined for four design parameters namely, delay(tp), power (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP). Moreover, MOS current mode logic (MCML) based implementation is investigated for NAND circuit. In addition to that, this paper also presents a smart logic design of MCML NAND based D flipflop. The broached design results as a competent candidate for countless D flipflop based digital logic designs as it relents exclusive results in contrast to the conventional counterpart. Thus, the proposed enactment broaches as ideal circuit for recent digital logic style applications.
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Suhail, R., Srivastava, P., Yadav, R., Srivastava, R. (2022). Power Efficient Analysis of MOS Current Mode Logic Based Delay Flip Flop. In: Lenka, T.R., Misra, D., Biswas, A. (eds) Micro and Nanoelectronics Devices, Circuits and Systems. Lecture Notes in Electrical Engineering, vol 781. Springer, Singapore. https://doi.org/10.1007/978-981-16-3767-4_33
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