Abstract
Complex binary number system (CBNS) finds extensive applications in the faster computation of various digital signal processing (DSP) algorithms. In this paper, an attempt has been undertaken to develop various computational circuits based on CBNS for implementation in Spartan XC3S700A FPGA platform. The circuits have been designed following a modular approach. The designed modules involve simple logic gates leading ultimately to efficient implementation on FPGA. The codes for the modules have been developed using verilog hardware description language (HDL). Structural-level designs of nibble size CBNS adder, multiplier, and subtractor have been exclusively accomplished involving these modules. In the design of multiplier and subtractor, a new concept of sub-block has been introduced to efficiently utilize the limited input capability of the designed modules. The proposed design involves less hardware complexity, silicon area, and path delay compared to existing works. Simulation results and performance metrics for all the three CBNS circuits have been included.
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References
Miguens MP, Chaves R, Sousa L (2015) Arithmetic-based binary-to-RNS converter modulo \(2^n pm k\) for jn -bit dynamic range. IEEE Trans VLSI Syst 23(3):603–607
Jamil T (2011) An introduction to complex binary number system. In: Processing of international conference on information and computing (ICIC), pp 229–232
Sengupta A, Natarajan B (2013) Performance of systematic RRNS based space-time block codes with probability-aware adaptive demapping. IEEE Trans Wirel Comm 12(5):2458–2469
Zhang S, Zhang Y, Yang LL (2011) Redundant residue number system based multicarrier DS-CDMA for dynamic multiple-access in cognitive radios. In: Processing of IEEE vehicular technology conference (VTC Spring), pp 1–5
Parhi M, Yingjie L, Parhi KK (2014) Canonic real-valued FFT structures. In: Processing of Asilomar conference on signals, systems and computers, pp 1261–1265
Knuth DE (1960) A imaginary number system, commun. ACM 3:245–247
Penney W (1965) A “binary”, systm for complex numbers. JACM 12(2):247–248
Jamil T, Holmes N, Blest D (2000) Towards implementation of a binary number system for complex numbers. In: Processing of IEEE southeastcon, pp 268–274
Jamil T (2002) The complex binary number system: basic arithmetic made simple. IEEE Potentials 20(5):39–41
Jamil T (2011) Design of arithmetic circuits for complex binary number system. J Am Inst Phys IAENG Trans Eng Technol 1373(1):83–97
Jamil T (2013) Complex binary number system algorithms and circuits. Springer, India, pp 5–6
Mukherjee M, Sanyal SK (2017) Design of CBNS nibble size adder using pass transistor logic circuit: extension to FPGA implementation. In: Communication and networking technologies. 8th international conference on computing. Delhi, India
Mukherjee M, Sanyal SK (2017) Design of a high-speed reconfigurable fast hartley transform processor using CBNS. In: 14th IEEE India council international conference. Roorkee, India
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Mukherjee, M., Sanyal, S.K. (2022). FPGA-Based Efficient Implementation of CBNS Computational Circuits: A Modular Approach. In: Mitra, M., Nasipuri, M., Kanjilal, M.R. (eds) Computational Advancement in Communication, Circuits and Systems. Lecture Notes in Electrical Engineering, vol 786. Springer, Singapore. https://doi.org/10.1007/978-981-16-4035-3_10
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DOI: https://doi.org/10.1007/978-981-16-4035-3_10
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