Abstract
The design of very large-scale integrated circuits passes through many critical stages and challenges the advanced technology of nanometer CMOS technology. The major problem included in the existing process is the leakage current and reliability issues. Penta-magnetic tunnel junction (Penta-MTJ) hybrid with CMOS technology has many advantages in the VLSI strategy such as higher performance and low leakage current. The methodology of the proposed work includes the increase in the storage capacity with optimized power and speed using transmission gate logic and decrease in area and power in combinational and sequential circuits. The structure of Penta-MTJ includes the design of transmission gates to increase the speed with the minimum number of gates to reduce the area and power consumption. By decreasing the number of transistors in transmission gate logic, the power consumption was reduced to 12 and 18%. To overcome the sensing reliability issue, high sensing margin is proposed in the design circuit. With a 43.9 and 10.7% increase in energy delay product (EDP), the proposed approach reduces energy demand while incurring low area overhead.
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References
Zabel H (2009) Progress in spintronics. Superlattices Microstruct 46(4):541–553
Grochowski E, Hoyt RF (1996) Future trends in hard disk drives. IEEE Trans Magn 32(3):1850–1854
Azzerboni B, Asti G, Pareti L, Ghidini M (eds) (2007) Magnetic nanostructures in modern technology: spintronics, magnetic MEMS and recording. Springer, Berlin
Sato M, Kobayashi K, Kikuchi H (1999) U.S. patent no. 5,986,858. U.S. Patent and Trademark Office, Washington, DC
Ohbayashi S, Yabuuchi M, Nii K, Tsukamoto Y, Imaoka S, Oda Y, Yamaguchi Y (2007) A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. IEEE J Solid-State Circuits 42(4):820–829
Chang CH, Gu J, Zhang M (2005) A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(6):686–695
Wang JM, Fang SC, Feng WS (1994) New efficient designs for XOR and XNOR functions on the transistor level. IEEE J Solid-State Circuits 29(7):780–786
Sirunyan AM, Backhaus M, Bäni L, Berger P, Bianchini L, Dissertori G, Hits D (2018) Identification of heavy-flavour jets with the CMS detector in pp collisions at 13 TeV. J Instrum 13:P05011
Prakash P, Saxena AK (2009) Design of low power high speed ALU using feedback switch logic. In: 2009 International conference on advances in recent technologies in communication and computing, October 2009. IEEE, p 899902
Sheu SS, Chang MF, Lin KF, Wu CW, Chen YS, Chiu PF, Lin CH (2011) A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160ns MLC-access capability. In: 2011 IEEE international solid-state circuits conference. IEEE, pp 200–202
Linder MC, Hazegh-Azam M (1996) Copper biochemistry and molecular biology. Am J Clin Nutr 63(5):797S-811S
Zhuang N, Wu H (1992) A new design of the CMOS full adder. IEEE J Solid-State Circuits 27(5):840–844
Zimmermann R, Fichtner W (1997) Low-power logic styles: CMOS versus pass-transistor logic. IEEE J Solid-State Circuits 32(7):1079–1090
Shams AM, Darwish TK, Bayoumi MA (2002) Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans Very Large Scale Integr (VLSI) Syst 10(1):20–29
Alioto M (2012) Ultra-low-power VLSI circuit design demystified and explained: a tutorial. IEEE Trans Circuits Syst I Regul Pap 59(1):3–29
Lee J, Mak KF, Shan J (2016) Electrical control of the valley hall effect in bilayer MoS 2 transistors. Nat Nanotechnol 11(5):421–425
Dayananda C, Sarada R, Rani MU, Shamala TR, Ravishankar GA (2007) Autotrophic cultivation of Botryococcus braunii for the production of hydrocarbons and exopolysaccharides in various media. Biomass Bioenerg 31(1):87–93
Truong DN, Cheng WH, Mohsenin T, Yu Z, Jacobson AT, Landge G, Work EW (2009) A 167-processor computational platform in 65 nm CMOS. IEEE J Solid-State Circuits 44(4):1130–1144
Aswini T, Reddy MM 18-nm low-power cascaded desıgn of penta MTJ-based dıgıtal cırcuıts usıng clock gatıng
Chen RKW, Gammel JC, Spires DA (1999) U.S. patent no. 5,881,129. U.S. Patent and Trademark Office, Washington, DC
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Manikandababu, C.S., Jagadeeswari, M., Manju, S., Aiswarya, M. (2022). Design and Analysis of Penta-Magnetic Tunnel Junction Circuit with Transmission Gate Logic. In: Bindhu, V., R. S. Tavares, J.M., Ţălu, Ş. (eds) Proceedings of Fourth International Conference on Inventive Material Science Applications. Advances in Sustainability Science and Technology. Springer, Singapore. https://doi.org/10.1007/978-981-16-4321-7_59
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DOI: https://doi.org/10.1007/978-981-16-4321-7_59
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