Implementation of UVM Agents for Hexagon Subsystem RTL

Abstract

Verification is a major bottleneck in the design of complex system designs, accounting for nearly 70% of the project development period. Directed test verification is currently a tedious, time-consuming, and repetitive task for verifying complex systems, and many uncovered scenarios will be left out. So, it is necessary to construct robust, scalable, and reusable SoC verification environment. Universal Verification Methodology (UVM) along with SystemVerilog work together to build a coverage-driven constrained random environment for verification. In this paper, UVM test bench is implemented for verifying the frequency generated from PLL, which in turn is used as the clock source for QDSP core, hence enhancing the reusability of verification components. PLLs (Phase Lock Loop) are an integral part in almost all SoCs, used as a frequency synthesizer. And the output of PLL is fed to the Clock Generator along with 2 different clock sources. Clock Generator is a mini clock macro used to generate the clock root which takes in 2 other raw clock sources. Clock Generator contains source muxing and clock divide (integer, half integer, fractional divide) ability.