Abstract
In this paper, high-speed latch comparator has been designed for the application of analog to digital converter (ADC). The circuit’s speed has been improved by a proposed comparator. It is designed with a supply voltage of 3.3 V at 180 nm CMOS technology at Cadence Virtuoso. By using the differential amplifier and latch design, a complete design for comparator is obtained.
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References
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Cho TB, Gray PR (1995) A10 b, 20 Msample/s, 35 mW pipeline A/D converter. Solid-State Circ IEEE J 30(3):166–172
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Pandey, K.M., Prajapati, Y.N., Kumar, N. (2022). Design of High-Speed Latched Comparator Used in Analog to Digital Converters by Using 180 nm Technology. In: Sharma, D.K., Peng, SL., Sharma, R., Zaitsev, D.A. (eds) Micro-Electronics and Telecommunication Engineering . ICMETE 2021. Lecture Notes in Networks and Systems, vol 373. Springer, Singapore. https://doi.org/10.1007/978-981-16-8721-1_20
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DOI: https://doi.org/10.1007/978-981-16-8721-1_20
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