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Improving Robustness of Two Speed Serial Parallel Booth Multiplier Using Fault Detection Mechanism

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Proceedings of Fourth International Conference on Communication, Computing and Electronics Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 977))

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Abstract

When it comes to circuit design, digital elements have a pivotal and crucial impact. Input values given to these components can be degraded by internal and external disturbances, it can happen either by virtue of foreign factors, to the lack of efficiency in the sensors, or maybe due to unknown lags in the communication systems. Hence, it is vital when the output responses related to these devices stay as robust when slightest fluctuations occur. Layout of robust components has been reported as primary challenge in the implementation of electronic systems. Ways to improve the robustness of circuits have been dealt with but either by adding huge amount of extra logic, alter the circuit latency, or these are suitable only for such circuits like microprocessors. Also, they suffer limitations by capturing application particular information of the circuit. However, the proposed methodology requires only a small increment in the extra hardware, which only affects the timing characteristics of the circuit in a less considerable manner, and will spontaneously apply to any of the circuits which are arbitrary.

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Correspondence to J. P. Anita .

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Nair, S.R., Anita, J.P. (2023). Improving Robustness of Two Speed Serial Parallel Booth Multiplier Using Fault Detection Mechanism. In: Bindhu, V., Tavares, J.M.R.S., Vuppalapati, C. (eds) Proceedings of Fourth International Conference on Communication, Computing and Electronics Systems . Lecture Notes in Electrical Engineering, vol 977. Springer, Singapore. https://doi.org/10.1007/978-981-19-7753-4_78

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  • DOI: https://doi.org/10.1007/978-981-19-7753-4_78

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