Abstract
NoC is a growing technology where interconnected patterns are developed in the state of multiprocessors. Due to the complicated routing links, many issues prevail regarding traffic congestion and latency which leads to the poor performance of a network. In this research work, Virtual router architecture is introduced which yields low latency resulting in improving the performance of a network. The proposed VIP-based VC architecture for a \(4\times 4\) mesh NoC has experimented for 128-bit wide system targeting up to 250 MHz using Xmulator. The experimental outcome exhibits a low latency that requires 500–600 cycles on an average with respect to other router architecture. This outperforms 33% of low latency when compared to the Wormhole router architecture.
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Sai Kumar, A., Hanumantha Rao, T.V.K. (2021). An Efficient Low Latency Router Architecture for Mesh-Based NoC. In: Laxminidhi, T., Singhai, J., Patri, S.R., Mani, V.V. (eds) Advances in Communications, Signal Processing, and VLSI. Lecture Notes in Electrical Engineering, vol 722. Springer, Singapore. https://doi.org/10.1007/978-981-33-4058-9_21
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DOI: https://doi.org/10.1007/978-981-33-4058-9_21
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