Abstract
Reversible Logic is an emerging field of research which finds its applications in low power computing, Nanotechnology and Quantum Computing. Reversible circuits should have one to one mapping i.e. one input can have only one output so that input vectors can be realized using output vectors. Reversible Circuits require Ancilla(constant inputs) and Garbage Outputs to retain reversibility. An efficient Reversible Circuit can be designed by optimizing their performance parameters. In this paper a \(4 \times 4\) Melior Quantum Multiplier has been proposed which consists of an optimized Partial Product Generation and Multi-Operand Addition using primitive Quantum gates to reduce the count of Ancilla and Garbage Outputs. This proposed multiplier shows an improvement of 21.73% and 18.18% reduction of Ancilla and Garbage Outputs respectively. This multiplier has been implemented in Cadence Virtuoso with average power dissipation of 106.79 nW at 45 nm technology node and used in the implementation of a Linear Phase FIR filter with an average power dissipation of 456.1 nW.
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Sai Roshan, R., Nawaz, S., Vuppala, A., Ravindra, J.V.R. (2021). Ultra Power Efficient Melior Quantum Multiplier with Reduced Ancilla and Garbage Outputs. In: Maji, A.K., Saha, G., Das, S., Basu, S., Tavares, J.M.R.S. (eds) Proceedings of the International Conference on Computing and Communication Systems. Lecture Notes in Networks and Systems, vol 170. Springer, Singapore. https://doi.org/10.1007/978-981-33-4084-8_64
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DOI: https://doi.org/10.1007/978-981-33-4084-8_64
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