Abstract
This paper presents a low-power ASIC architecture of a feedforward Artificial Neural Network using Posit representation. The ASIC Posit shows 50% improvement over ASIC using IEEE 754 format in terms of Power and Silicon Area and is also 13% faster while achieving the same accuracy. The same design using the FPGA platform consumes more power than the ASIC design. The designs are done using Cadence RTL Encounter with TSMC 180 nm technology node.
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Gupta, A., Gupta, A., Gupta, R. (2023). Efficient ASIC Implementation of Artificial Neural Network with Posit Representation of Floating-Point Numbers. In: Bansal, H.O., Ajmera, P.K., Joshi, S., Bansal, R.C., Shekhar, C. (eds) Next Generation Systems and Networks. BITS-EEE-CON 2022. Lecture Notes in Networks and Systems, vol 641. Springer, Singapore. https://doi.org/10.1007/978-981-99-0483-9_5
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DOI: https://doi.org/10.1007/978-981-99-0483-9_5
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