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Design and Analysis of CIC Decimation Filter Using Redundant Number System

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VLSI, Communication and Signal Processing (VCAS 2022)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 1024))

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Abstract

The multirate transformation is a frequently used method for decimation and interpolation in real-time digital signal processing. In wireless applications, comb-based decimation filters are used because of their high alias elimination and low complexity. A symmetrical FIR filter, namely a cascaded integrator-comb (CIC) filter, can be utilized as a decimation filter. Since this filter does not have a multiplier, it requires fewer hardware resources and has a higher speed than other decimation filters. The main considerations in design objectives for current digital signal processing (DSP) applications are optimization of power, speed and hardware resources. The redundant number system is used in digital systems to reduce computational load, and this efficiency can then be further improved by modifying the architecture at the circuit level. Thus, the signed digit-based FIR filter is proposed as a compensation filter that reduces the passband droop and increases the attenuation in the folding band. Based on the proposed compensation filter with CIC filter design, a reduction in passband droop of 17.27 \(\%\) and improvement in attenuation in the folding band of 12.29 \(\%\) are achieved in comparison with the existing structure. In addition, the simulation results show a decrease in LUTs utilized of 10.44 \(\%\) in comparison with the existing design.

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Authors and Affiliations

  1. Harcourt Butler Technical University, Kanpur, India

    Ajeet Kumar Srivastava & Krishna Raj

  2. C S J M University, Kanpur, India

    Alok Kumar

Authors
  1. Ajeet Kumar Srivastava
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  2. Krishna Raj
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  3. Alok Kumar
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Corresponding author

Correspondence to Ajeet Kumar Srivastava .

Editor information

Editors and Affiliations

  1. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh, India

    R. K. Nagaria

  2. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh, India

    V. S. Tripathi

  3. Department of Electrical, Electronic and Communications Engineering, Public University of Navarra (UPNA), Pamplona, Spain

    Carlos Ruiz Zamarreno

  4. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh, India

    Yogendra Kumar Prajapati

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Srivastava, A.K., Raj, K., Kumar, A. (2023). Design and Analysis of CIC Decimation Filter Using Redundant Number System. In: Nagaria, R.K., Tripathi, V.S., Zamarreno, C.R., Prajapati, Y.K. (eds) VLSI, Communication and Signal Processing. VCAS 2022. Lecture Notes in Electrical Engineering, vol 1024. Springer, Singapore. https://doi.org/10.1007/978-981-99-0973-5_56

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  • DOI: https://doi.org/10.1007/978-981-99-0973-5_56

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-99-0972-8

  • Online ISBN: 978-981-99-0973-5

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