Abstract
In this work, we provide three novel magnitude comparators that operate on a minimal amount of power. A comparator is a mechanism that may be used to make decisions, and it has the potential to be implemented in a variety of control modules. In comparison to those of the currently available two-bit comparator designs, those currently being proposed for use with two-bit comparators dissipate less power, offer less propagation delay and spend less energy overall. Out of all the offered designs of comparator, the proposed design II is the one that uses the least amount of power and energy, whilst the proposed design III offers the least amount of delay and requires the least amount of space. With the assistance of the Synopsys HSPICE tool, a statistical comparison between the proposed circuits and the existing ones is carried out in terms of power losses, latency, transistor count and power delay product.
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Rajput, A., Dua, T., Gour, S., Kumawat, R. (2023). Novel Two-Bit Magnitude Comparators for IOT Applications. In: Rathore, V.S., Piuri, V., Babo, R., Ferreira, M.C. (eds) Emerging Trends in Expert Applications and Security. ICETEAS 2023. Lecture Notes in Networks and Systems, vol 682. Springer, Singapore. https://doi.org/10.1007/978-981-99-1946-8_44
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DOI: https://doi.org/10.1007/978-981-99-1946-8_44
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