Abstract
The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.
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This work is supported by the Ministry of Education of Spain (CICYT TIC 046/95).
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Segura, J., De Benito, C., Rubio, A. et al. A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. J Electron Test 8, 229–239 (1996). https://doi.org/10.1007/BF00133386
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DOI: https://doi.org/10.1007/BF00133386