Abstract
This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part of a self-checking circuit. The input encoding algorithm can be applied to any circuit without significantly increasing the input lines. The output encoding technique involves graph-embedding which is done with heuristic method of polynomial complexity. The heuristic technique produces nearly optimal output encoding. Previously published work restrict the types of gates used in the circuit to non-inversion gates (AND/OR), and use inverters only at the inputs. The proposed techniques have a clear advantage over the currently available techniques because they allow the use of any types of gates. These techniques do not necessarily increase the overhead when applied to different MCNC benchmark circuits as the experimental results indicate. The only restriction is that either the inputs or the outputs have to be symbolic, and the two-level description of a circuit has to be given.
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References
Y. Savaria, N.C. Rumin, J. Hayes, and V. Agarwal, “Soft-error filtering: A solution to the reliability problem of future VLSI logic circuits,”IEEE Proc., vol. 74, pp. 669–683, May 1986.
M. Yen, W. Fuchs, and J. Abraham, “Designing for concurrent error detection in VLSI: Application to a microprogram control unit,”IEEE Journal of Solid-State Circuits, vol. SC-22, pp. 595–605, Aug. 1987.
J. Smith and G. Metze. “The Design of Totally Self-Checking Combinational Circuits,”Proc. Intl. Symp. Fault-Tolerant Computing, Los Angeles, CA, pp. 130–134, June 1977.
M. Diaz, “Design of Totally Self-Checking and Fail Safe Sequential Machines,”Proc. Intl. Symp. Fault-Tolerant Computing, Urbana, IL, pp. 9–24, June 1974.
J. Smith and P. Lam, “A theory of totally self-checking system design,”IEEE Trans. on Computers, vol. C-32, pp. 831–844, Sept. 1983.
C. Frieman, “Optimal error detecting codes for completely asymmetric binary channels,”Information and Control, vol. 5, pp. 64–71, March 1962.
H. Dong, “Modified Berger codes for detection of unidirectional errors,”Proc. Intl. Symp. Fault-Tolerant Comput., Santa Clara, CA, pp. 317–320, June 1982.
S. Devadas, H.T. Ma, A.R. Newton, and A.L. Sangiovanni-Vincentelli, “Irredundant sequential machines via optimal logic synthesis,”IEEE Trans. Computer-Aided Design, vol. 9, pp. 8–17, Jan. 1990.
S. Devadas and K. Keutzer, “A unified approach to the synthesis of fully testable sequential machines,”IEEE Trans. Computer-Aided Design, vol. 10, pp. 39–50, Jan. 1991.
R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, “MIS: A multiple-level logic optimization program,”IEEE Trans. on Computer-Aided Design, vol. 7, pp. 1062–1081, Nov. 1987.
S. Devadas and A.R. Newton, “Exact algorithms for output encoding, state assignment and four-level Boolean minimization,”IEEE Trans. Computer-Aided Design, vol. 10, pp. 13–27, Jan. 1991.
K. Keutzer, S. Malik, and A. Saldanha, “Is redundancy necessary to reduce delays?”IEEE Trans. Computer-Aided Design, vol. 10, pp. 427–435, April 1991.
K. Bartlett, R.K. Brayton, G.D. Hachtel, R.J. Jacoby, C.R. Morrison, R.L. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, “Multi-level logic minimization using implicit don't cares,”IEEE Trans. Computer-Aided Design, vol. 7, pp. 723–740, June 1988.
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This work was supported in part by the Advanced Research Projects agency (ARPA) under grant N00600-93-K-2501.
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Busaba, F.Y., Lala, P.K. Self-checking combinational circuit design for single and unidirectional multibit error. J Electron Test 5, 19–28 (1994). https://doi.org/10.1007/BF00971960
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DOI: https://doi.org/10.1007/BF00971960