Abstract
The main problems that are the major concern in network testing are fault detection, fault location, and fault prediction. In this paper a multiple-fault-prediction algorithm is proposed for analog circuits with inaccessible nodes. The components in the circuits may be nominals or may be deviated from the nominals within a prescribed tolerance.
In the proposed prediction algorithm, the component values are evaluated according to the consecutive voltage measurements that are continuously monitored at the accessible test points at each periodic maintenance. The component values are used to locate the faulty components and/or to predict the components that are about to fail.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
J. W. Bandler and A. E. Salama, Fault diagnosis of analog circuits,IEEE Proc.,73, 1279–1325, 1985.
T. N. Trick and C. J. Alajajian, Fault analysis of analog circuits,Proceedings of the 20th Midwest Symposium on Circuits and Systems, Lubbock, TX, pp. 211–215, 1977.
A. A. Sakla, E. I. El-Masry, and T. N. Trick, A sensitivity algorithm for fault detection in analog circuits,Proceedings IEEE 1980 International Symposium on Circuits and Systems, Houston, TX, pp. 1075–1077, 1980.
Z. F. Huang, C. S. Lin, and R. W. Liu, Node-fault diagnosis and a design of testability,IEEE Trans. Circuits and Systems,30, 257–265, 1983.
R. M. Biernacki and J. W. Bandler, Fault location of analog circuits,Proceedings of the 1980 IEEE International Symposium on Circuits and Systems, Houston, TX, pp. 1078–1081, 1980.
R. M. Biernacki and J. W. Bandler, Multiple-fault location in analog circuits,IEEE Trans. Circuits and Systems,28, 361–366, 1981.
J. W. Bandler, R. W. Biernacki, A. E. Salama, and J. A. Starzyk, Fault isolation in linear analog circuits using the L1 norm,Proceedings of the 1982 International Symposium on Circuits and Systems, Rome, pp. 1140–1143, 1982.
C.-C. Wu, K. Nakajima, C. L. Wey, and R. Saeks, Analog fault diagnosis with failure bounds,IEEE Trans. Circuits and Systems,29, 277–284, 1982.
C. L. Wey and R. Saeks, On the implementation of analog ATPG: the linear case,IEEE Trans. Instrumentation and Measurement,34, 442–449, 1985.
R. J. Allen, Failure prediction employing continuous monitoring techniques,IEEE Trans. Aerospace Support Conf. Proc.,1, 924–930, 1963.
L. Tung and R. Saeks, An experiment in fault prediction,Proceedings of the Fourth Symposium on Reliability in Electronics, Budapest, pp. 249–257, 1977.
R. Saeks, An experiment in fault prediction, II,Proceedings of the 1976 IEEE AUTOTESTCON, Arlington, TX, p. 53, 1976.
S. R. Liberty, L. Tung, and R. Saeks, Fault prediction—toward a mathematical theory, inRational Fault Analysis, pp. 135–142, Marcel Dekker, New York, 1977.
R. Saeks, An approach to built-in testing,IEEE Trans. Aerospace Electron. Systems,14, 813–818, 1978.
B. L. Jiang and C. L. Wey, Multiple fault diagnosis with failure bounds for analog circuits,Proceedings of the IEEE 1986 International Symposium on Circuits and Systems, San Jose, CA, pp. 1261–1264, 1986.
B. L. Jiang, Ph.D. dissertation, Michigan State University (in preparation).
Author information
Authors and Affiliations
Additional information
This research was supported in part by AURI, Michigan State University, East Lansing, Michigan, and in part by Michigan Research Excellence/Economic Development Fund.
Rights and permissions
About this article
Cite this article
Jiang, B.L., Wey, C.L. & Fan, L.J. Fault prediction for analog circuits. Circuits Systems and Signal Process 7, 95–109 (1988). https://doi.org/10.1007/BF01600009
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF01600009