Abstract
This review deals with the theory and practice of discrete automata, especially with transition processes and hazardous races in such automata.
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Literature cited
L. Al'tman, “Modern achievements in the domain of logic IC and LSI,” Elektronika, No. 4, 25–55 (1974).
A. A. Ambartsumyan, “Automatic designing of discrete control devices for engineeringtransport equipment on the basis of the FORUM language,” in: Coll. Sci. Proceed, Chelyabinsk Polytechnical Inst., No. 138, 36–43 (1973).
A. N. Anishchenko and A. E. Yankovskaya, “Detection and elimination of static races,” Second All-Union Conference on the Theory of Relay Devices and Finite Automata, Abstracts of Reports, Riga (1971), pp. 179–180.
A. G. Astanovskii, L. Ya. Rozenblyum, N. A. Starodubtsev, R. L. Finkel'shtein, and B. S. Tsirlin, “Computing and control circuits based on aperiodic automata with self-synchronization,” in: Discrete Systems, Vol. 4, Zinatne, Riga (1974), pp. 68–78.
I. N. Bukreev, B. M. Mansurov, and V. I. Goryachev, Microelectronic Circuits of Digital Devices [in Russian], Sovet-skoe Radio, Moscow (1973).
V. I. Varshavskii, “Aperiodic automata with self-synchronization,” in: Discrete Systems, Vol. 1, Zinatne, Riga (1974), pp. 9–25.
I. S. Vizirev, “On the stability of an asynchronous finite automaton,” in: Discrete Systems, Vol. 1, Zinatne, Riga (1974), pp. 94–103.
I. S. Vizirev, “Reducing the number of delays in the realization of an asynchronous finite automaton,” Avtomat. Vychisl. Tekh., No. 1, 1–6 (1973).
I. S. Vizirev and A. F. Petrenko, “Elimination of hazardous logic races in the design of asynchronous automata,” Avtomat. Vychisl. Tekh., No. 3, 1–9 (1975).
M. A. Gavrilov and V. V. Devyatkov, “Peculiar features of logic design in DASP system,” in: Abstract and Structural Theory of Relay Devices, Nauka, Moscow (1975), pp. 5–7.
M. A. Gavrilov, V. M. Ostianu, and A. I. Potekhin, “Reliability of discrete systems,” in: Teoriya Veroyatnostei. Mat. Statistika. Teor. Kibernetika, 1969. (Itogi Nauki. VINITI AN SSSR), Moscow (1970), pp. 7–104.
A. Yu. Gobzemis, “Design of asynchronous finite automata with feedback logic,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 2, Varna (1971), pp. 263–268.
A. Yu. Gobzemis, “Design of asynchronous finite automata based on a model with feedback logic,” in: Problems of Design of Finite Automata, Zinatne, Riga (1972), pp. 3–8.
A. Yu. Gobzemis, “Design of asynchronous automata using universal modules,” in: Theory of Finite Automata and Its Applications, No. 4, Zinatne, Riga (1975), pp. 3–11.
A. Yu. Gobzemis and V. P. Chapenko, “Coding of internal states of automata taking into account the relationship between the delays of memory elements,” Avtomat. Vychisl. Tekh., No. 6, 14–18 (1973).
V. G. Gorobets, “Certain algorithms of distribution of asynchronous finite automata designed on the basis of universal unifunctional elements,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 1, Varna (1971), pp. 136–143.
V. G. Gorobets, “Design of asynchronous finite automata on the basis of homogeneous arrays,” in: Problems of Design of Finite Automata, Zinatne, Riga (1972), pp. 55–63.
D. R. Grinbaum, “Models of digital IC for computer-aided design, Review, Part I, TTL NAND gates,” Elektronika, No. 25, 46–52 (1973).
D. R. Grinbaum and V. A. Miller, “Models of digital IC for computer-aided design, Review, Part II, Elektronika, No. 26, 67–73 (1973).
D. R. Grinbaum and V. A. Miller, “Models of digital IC for computer-aided design, Review, Part IV, AND-OR-NOT gates,” Elektronika, No. 3, 55–58 (1974).
G. K. Deksnis, “Certain problems of coding of the internal states of asynchronous finite automata,” in: Problems of Design of Finite Automata, Zinatne, Riga (1972), pp. 9–19.
E. L. Denisenko, “On a method for reducing the dimension of the problem of antirace coding of the states of an asynchronous automaton by decomposing it,” in: Automation of the Logic Design of Digital Devices, Kiev (1973), pp. 86–93.
N. B. Doncheva and I. S. Vizirev, “Algorithmic realization of finite automaton in homogeneous array,” in: Discrete Systems, Vol. 3, Zinatne, Riga (1974), pp. 205–214.
A. D. Zakrevskii, Algorithms of Design of Discrete Automata [in Russian], Nauka, Moscow (1971).
A. D. Zakrevskii, Computer-Aided Design of Asynchronous Automata [in Russian], Nauka i Tekhnika, Minsk (1975).
A. D. Zakrevskii, A. N. Anishchenko, L. I. Balaklei, N. A. Eliseeva, A. M. Oralov, L. D. Pikhtova, Yu. V. Pottosin, N. R. Toropov, and A. E. Yankovskaya, “The AVTOMAT-3 system of automatic design of discrete automata,” in: Discrete Systems, Vol. 3, Zinatne, Riga (1974), pp. 84–92.
A. D. Zakrevskii, Yu. M. Komarov, and A. E. Yankovskaya, “Neighbor coding of internal states of asynchronous automata,” in: Discrete Systems, Vol. 1, Zinatne, Riga (1974), pp. 104–112.
A. D. Zakrevskii, Yu. V. Pottosin, V. F. Rotko, N. R. Toropov, and A. E. Yankovskaya, “Systems and programs of design of discrete devices, a system of automatic design of discrete automata,” Inform. Materials Science Council for the Complex Problem of Cybernetics at the Acad. Sci. USSR, No. 7(54) (1971), pp. 42–62.
A. D. Zakrevskii and A. E. Yankovskaya, “Noiseproof coding of internal states of asynchronous automata,” Inform. Materials Science Council for the Complex Problem of Cybernetics at the Acad. Sci. USSR, No. 3(50) (1971), pp. 53–58.
I. G. Ilzinya and G. F. Fritsnovich, “Coding of internal states of asynchronous finite automata by P-code,” Avtomat. Vychisl. Tekh., No. 6, 5–11 (1970).
M. A. Kaevchenko, “Coding of asynchronous finite automata,” (Editorial Board of Journal Avtomatika i Vychisl. Tekhn. Acad. Sci. LatSSR), Riga (1973). (Manuscript deposited at VINITI on Dec. 11, 1973, No. 7550-73 Dep.)
V. V. Karyos and A. F. Petrenko, “Coding of states of asynchronous automata based on two-stage memory model,” in: Theory of Finite Automata and Its Applications, No. 1, Zinatne, Riga (1973), pp. 35–46.
Ya. N. Kobrinskii and N. N. Zubov, “Ensuring stability in potential logic networks. I,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 6, 149–159 (1972).
V. M. Kopylenko, “Design of race-free circuits in the logic part of a relay device,” in: Design Principles and Methods of Synthesis of Operating Units of Remote-Control Systems, Ilim, Frunze (1971), pp. 22–31.
A. G. Lebedev and A. I. Potekhin, “Algorithm of coding of internal states of relay devices,” in: Abstract and Structural Theory of Relay Devices, Nauka, Moscow (1972), pp. 147–157.
R. Miller, Theory of Switching Circuits. II. Sequential Networks and Machines [Russian translation], Nauka, Moscow (1971).
N. V. Mon'kov, “On a problem of structural design of asynchronous finite automata,” Collect. Papers Leningrad Inst. Railway Engineering Transport, No. 312 (1970), pp. 65–72.
Yu. E. Naumov, N. A. Avaev, and M. A. Bedrekovskii, Noise Immunity in Integrated Logic Circuits [in Russian], Sov. Radio, Moscow (1975).
A. A. Nikanorov, M. S. Pinsker, and Yu. L. Sagalovich, “Peculiar features of redundancy limits for state codes of automata,” in: Discrete Systems, Vol. 4, Zinatne, Riga (1974), pp. 217–220.
V. Onzul, “Functional races in combinational logic circuits,” Proceed. International Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 2, Varna (1971), pp. 295–302.
A. F. Petrenko, “Method of coding of internal states of asynchronous finite automata,” in: Vychisl. Tekhnika, Vol. 3, Kaunas (1972), pp. 52–53.
A. F. Petrenko, “Minimization of length of code of internal states of asynchronous finite automata with two-stage memory,” in: Problems of Design of Finite Automata, Zinnatne, Riga (1972), pp. 21–26.
A. F. Petrenko, “Model of asynchronous finite automaton with three-stage memory,” Avtomat. Vychisl. Tekh., No. 5, 1–6 (1971).
A. F. Petrenko, “Models of asynchronous finite automata,” Avtomat. Vychisl. Tekh., No. 4, 1–13 (1973).
A. F. Petrenko, “On the realization of asynchronous automata with delays,” in: Problems of Design of Digital Computer Logic, Part 2, Vilnius (1974), pp. 24–29.
A. F. Petrenko, “Using the simplicity of structure in coding the internal states of an asynchronous automaton by a direct code,” Avtomat. Vychisl. Tekh., No. 1, 19–22 (1972).
A. F. Petrenko and G. F. Fritsnovich, “Design of asynchronous finite automata taking into account a reduction in the number of filters,” Avtomat. Vychisl. Tekh., No. 6, 19–22 (1972).
E. I. Piil', “Coding of states of microprogram automata,” in: Discrete Automata and Communication Networks, Nauka, Moscow (1970), pp. 57–65.
M. S. Pinsker and Yu. L. Sagalovich, “Memory capacity of an automaton that is stable with respect to damage and races of delay elements,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 2, Varna (1971), pp. 315–324.
M. S. Pinsker and Yu. L. Sagalovich, “Lower bound for power of code of automata states,” Probl. Peredachi Inf.,8, No. 3, 58–66 (1972).
A. I. Potekhin, “A method of design of asynchronous automata,” in: Discrete Systems, Vol. 1, Zinatne, Riga (1974), pp. 222–230.
A. I. Potekhin, “A method of transformation of the transition graph of a relay device into a partial subgroup of an n-dimensional unit cube,” in: Optimization of Operations Research., Bionics, Nauka, Moscow (1973), pp. 138–144.
V. N. Roginskii, Foundations of Discrete Automation [in Russian], Svyaz', Moscow (1975).
Yu. L. Sagalovich, Coding of States and Reliability of Automata [in Russian], Svyaz', Moscow (1975).
V. V. Sapozhnikov and Vl. V. Sapozhnikov, “Obtaining of switching functions of memory elements of finite automata in the case of state coding according to transition table columns,” Probl. Peredachi Inf.,9, No. 4, 90–91 (1973).
V. V. Sapozhnikov and Vl. V. Sapozhnikov, “Design of asynchronous finite automata that are stable with respect to damage of elements of logic converter,” Avtomat. Vychisl. Tekh., No. 3, 39 (1974).
V. V. Sapozhnikov and Vl. V. Sapozhnikov, “Standard realization of relay device,” Avtomat. Vychisl. Tekh., No. 1, 13–16 (1971).
I. D. Seifulla, “Elimination of critical races in an asynchronous automaton realized in a homogeneous matrix array,” in: Automata and Control, Nauka, Moscow (1972), pp. 35–38.
I. D. Seifulla, A. V. Solov'ev, and V. G. Chernyaev, “Algorithm of design of asynchronous automata in a homogeneous matrix array,” in: Design of Automata and Control in Communication Networks, Nauka, Moscow (1973), pp. 67–72.
A. A. Tal' and S. A. Yuditskii, “Description and synthesis of asynchronous discrete devices,” in: Discrete Systems, Vol. 1, Zinatne, Riga (1974), pp. 242–251.
Yu. L. Tomfel'd, “On logic races in faulty circuits,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 2, Varna (1971), pp. 420–429.
T. L. Frantsis, “Design of asynchronous time automata with delays,” in: Problems of Design of Finite Automata, Zinatne, Riga (1972), pp. 65–71.
G. F. Fritsnovich, “Coloring of graph vertices used for optimizing the design of asynchronous finite automata,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 1, Varna (1971), pp. 118–127.
G. F. Fritsnovich, “Coding of internal states of asynchronous finite automata by an ncode of minimal length,” in: Theory of Finite Automata and Its Applications, No. 1, Zinatne, Riga (1973), pp. 23–24.
G. N. Fritsnovich and M. I. Yakobzon, “Coloring of graph vertices used for coding of states of asynchronous finite automata,” in: Problems of Design of Finite Automata, Zinatne, Riga (1972), pp. 41–46.
E. A. Kholina, “Analysis and elimination of races in two-level logic circuits,” in: Theory of Finite Automata and Its Applications,” No. 2, Zinatne, Riga (1973), pp. 46–52.
V. G. Chernyaev, “Problems of stable operation of automata in a homogeneous matrix array,” in: Third Conference on Logic Design in Discrete Homogeneous Arrays, 1974, Abstracts of Reports, Ryazan (1974), pp. 110–112.
V. G. Chernyaev, “On the design of stable modular circuits of asynchronous automata,” in: Automata and Control, Nauka, Moscow (1972), pp. 40–44.
V. G. Chernyaev, “Neighbor coding and the design of stable modular automata circuits,” in: Design of Control Devices and Systems, Nauka, Moscow (1974), pp. 49–58.
D. B. Shishkov, “Canonical realization of automata,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 1, Varna (1971), pp. 238–248.
É. A. Yakubaitis, “Irredundant coding of internal states of finite automata,” in: Automata, Hybrid and Control Computers, Nauka, Moscow (1972), pp. 79–88.
É. A. Yakubaitis, “Integrated model of discrete devices,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 1, Varna (1971), pp. 46–64.
É. A. Yakubaitis, “Singular states of cyclic model of discrete devices,” Avtomat. Vychisl. Tekh., No. 4, 1–5 (1971).
É. A. Yakubaitis, Design of Asynchronous Finite Automata [in Russian], Zinatne, Riga (1970).
É. A. Yakubaitis, “Synchronized finite automata,” Avtomat. Vychisl. Tekh., No. 3, 1–8 (1973).
É. A. Yakubaitis, “Synchronized model of discrete devices,” Avtomat. Vychisl. Tekh., No. 4, 14–21 (1973).
É. A. Yakubaitis, “Stable coding of states of cyclic model of discrete devices,” Avtomat. Vychisl. Tekh., No. 2, 1–6 (1972).
É. A. Yakubaitis, V. O. Vasyukevich, A. Yu. Gobzemis, N. E. Zaznova, A. A. Kurmit, A. A. Lorents, A. F. Petrenko, and V. P. Chapenko, “Theory of automata,” in: Teoriya Veroyatnostei, Mat. Statistika, Teor. Kibernetika,13 (Itogi Nauki i Tekhniki. VINITI AN SSSR), Moscow (1976), pp. 109–188.
É. A. Yakubaitis and A. Yu. Gobzemis, “Coding of internal states of asynchronous finite automata with two-stage memory,” Avtomat. Vychisl. Tekh., No. 6, 1–4 (1970).
É. A. Yakubaitis, A. Yu. Gobzemis, A. F. Petrenko, and G. F. Fritsnovich, “On the design of asynchronous finite automata,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 6, 139–148 (1972).
É. A. Yakubaitis and A. F. Petrenko, “Reducing the number of memory elements of a cyclic model of discrete devices,” Avtomat. Vychisl. Tekh., No. 1, 1–5 (1972).
A. E. Yankovskaya, “Coding algorithms for internal states of asynchronous automata,” in: Digital Models and Integrating Structures, Taganrog (1970), pp. 371–380.
V. Batra, “Design of asynchronous unit delays,” IEEE Trans. Comput.,19, No. 10, 896–902 (1970).
J. Bredeson, “On multiple input change hazard-free combinational switching circuits without feedback,” IEEE 14th Annual Symp. Switch. and Automata Theory, 1973, Northridge, Calif. (1973), pp. 56–63.
J. Bredeson and P. T. Hulina, “Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits,” Inf. Control,20, No. 2, 114–124 (1972).
J. Bruno and S. M. Altman, “A theory of asynchronous control networks,” IEEE Trans. Comput.,20, No. 6, 629–638 (1971).
H. Y. H. Chuang and Das Santanu, “Synthesis of multiple-input change asynchronous machines using controlled excitation and flip-flops,” IEEE Trans. Comput.,22, No. 12, 1103–1109 (1973).
R. David and P. Deschizeaux, “Automatic synthesis of asynchronous sequential networks with universal cells,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 1, Varna (1971), pp. 144–156.
R. David, J. C. Laurent, and R. Perret, “Principle and realization with MOS technology of a universal cell for asynchronous sequences,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 1, Varna (1971), pp. 157–170.
E. G. DuCasse and G. A. Metze, “Hazard-free realizations of Boolean functions using Post functions,” Conf. Rec. Int. Symp. Multiple-Valued Logic, Toronto, 1973, S. 1, 59–67 (1973).
D. Elhadef and E. Smith, “State assignment for multiple-output-change asynchronous sequential machines,” Proc. Sixth Annual Southeast Symp. Syst. Theory, Baton Rouge, La., 1974, FA-4, No. 1, 1–3, Baton Rouge, La.
A. D. Friedman, R. L. Graham, and J. D. Ullman, “Universal single transition time asynchronous state assignments,” IEEE Trans. Comput.,18, No. 6, 541–547 (1969).
G. Frosini, “Influence of state reduction of the number of state variables in racefree asynchronous sequential circuits,” Inf. Control,20, No. 1, 55–68 (1972).
G. Frosini and G. Gerace, “A universal STT state assignment method for pulse input asynchronous sequential circuits,” IEEE Trans. Comput.,20, No. 8, 856–861 (1971).
G. Frosini and G. Gerace, “Master-slave realization of asynchronous sequential circuits,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Varna (1971), pp. 214–237.
G. Frosini and G. Gerace, “Pulse input asynchronous sequential circuits,” IEEE Trans. Comput.,20, No. 4, 437–442 (1971).
J. C. Geffroy, “Totally left-testing asynchronous sequential circuits,” in: Discrete Systems, Vol. 2, Zinatne, Riga (1974), pp. 134–143.
R. Hackbart and D. Dietmeyer, “The avoidance and elimination of function hazards in asynchronous sequential circuits,” IEEE Trans. Comput.,20, No. 2, 184–189 (1971).
G. Hallbauer, “On the RENDIS-C program system for race-free and optimal coding of internal states of sequential circuits,” 18th Int. Sci. Colloq. Techn. Hochsch. Ilmenau, No. 4, 77–80, S. 1, s. a. (1973).
P. T. Hulina and J. G. Bredeson, “Synthesis of asynchronous sequential circuits using race-resistant flip-flops,” Proc. 5th Annual Princeton Conf. Inform. Sci. and Syst., Princeton, N. J., 307–314 (1971).
J. R. Jump, “Asynchronous control arrays,” IEEE Trans. Comput.,23, No. 10, 1020–1029 (1974).
H. Kamionka-Mikula, “Design of hazard-free minimal sequential TANT control systems,” Arch. Automat, e Telemech.,19, No. 2, 183–197 (1974).
A. Kandel, “Note on hazard elimination,” IEEE Trans. Comput.,22, No. 10, 955–956 (1973).
R. S. Kashef, “On the race-free assignment and classification of asynchronous sequential machines,” Proc. 5th Hawai Int. Conf. Syst. Sci., Honolulu, Haw., 1972 (Hollywood, Calif.) (1972), pp. 459–462.
R. S. Kashef and R. B. McGhee, “Augmented parity check codes for encoding of asynchronous sequential machines,” IEEE Trans. Comput.,22, No. 10, 891–896 (1973).
Izumi Kimura, “Space-continuous time-semicontinuous theory of speed-independent asynchronous circuits,” Inf. Control,22, No. 4, 373–393 (1973).
L. K. Larry, “A characterization of some asynchronous sequential networks and state assignments,” IEEE Trans. Comput.,20, No. 4, 426–436 (1971).
G. Magö, “Asynchronous sequential circuits with (2, 1) type state assignments,” IEEE Conf. Rec. 11th Annual Symp. Switch. and Automata Theory, Santa Monica, Calif., 1970, New York, N. Y. (1970), pp. 109–113.
G. Magó, “Monotone functions in sequential circuits,” IEEE Trans. Comput.,22, No. 10 928–933 (1973).
G. Magó, “Realization methods for asynchronous sequential circuits,” IEEE Trans. Comput.,20, No. 3, 290–297 (1971).
G. K. Maki and D. H. Sawin, “Asynchronous sequential circuits capable of detecting and tolerating single faults,” FTC/3. Int. Symp. Fault-Tolerant Comput., Palo Alto, Calif., 1973, Dig. Pap. New York, N. Y. (1973), 151–156.
G. K. Maki and D. H. Sawin, “Fault-tolerant asynchronous sequential machines,” IEEE Trans. Comput.,23, No. 7, 651–657 (1974).
G. Maki and J. H. Tracey, “State assignment selection in asynchronous sequential circuits,” IEEE Trans. Comput.,19, No. 7, 641–644 (1970).
G. Maki, J. H. Tracey, and R. J. Smith, “Generation of design equations in asynchronous sequential circuits,” IEEE Trans. Comput.,18, No. 5, 467–470 (1969).
L. L. Maté, Das Santanu, and H. Y. H. Chuang, “A logicl hazard detection and elimination method,” Inf. Control,26, No. 4, 351–368 (1974).
G. Moraga and J. Gutiérrez, “Critical races in fundamental mode ternary sequential machines,” Proc. Int. Symp. Multiple-Valued Logic, Morgantown, W. Va., 1974, 401–411 (1974).
Yuzo Mukai and Yoshihiro Tohma, “A method for the realization of fail-safe asynchronous sequential circuits,” IEEE Trans. Comput.,23, No. 7, 736–739 (1974).
Katsuhiko Nakamura, “Asynchronous cellular automata and their computational ability,” Densi Tsusin Gakkai Rombunsi, Trans. Inst. Electr. Commun. Eng. Jpn.,D57, No. 10, 573–580 (1974).
W. W. Patterson and G. Metze, “A fail-safe asynchronous sequential machine,” IEEE Trans. Comput.,23, No. 4, 369–374 (1974).
W. W. Patterson and G. Metze, “A fault-tolerant asynchronous sequential machine,” Dig. Pap. Int. Symp. Fault-Tolerant Comput., Newton, Mass., 1972, New York, N. Y. (1972), pp. 176–181.
D. K. Pradhan and S. M. Reddy, “Fault-tolerant asynchronous networks,” IEEE Trans. Comput.,22, No. 7, 662–669 (1973).
C. A. Rey, “Self-synchronized combinational circuits,” Inform. Process. 74, 168–170, Amsterdam-London (1974).
C. A. Rey and J. Vaucher, “Self-synchronized asynchronous machines,” IEEE Trans. Comput.,23, No. 12, 1306–1311 (1974).
K. Sapilcha, “Elimination of M-races in realizations of partially determined Boolean functions,” Arch. Automat. Telemech.,19, No. 2, 199–205 (1974).
G. Saucier, “Assignment and next equations of asynchronous sequential machines,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 2, Varna (1971), pp. 325–332.
G. Saucier, “Next-state equations of asynchronous machines,” IEEE Trans. Comput.,21, No. 4, 397–399 (1972).
G. Saucier, “State assignment of asynchronous sequential machines using graph techniques,” IEEE Trans. Comput.,21, No. 3, 282–288 (1972).
D. H. Sawin and G. K. Maki, “Asynchronous sequential machines designed for fault detection,” IEEE Trans. Comput.,23, No. 3, 239–249 (1974).
D. H. Sawin and S. R. Groenig, “Design of asynchronous sequential machines for fault detection,” Dig. Pap. Int. Symp. Fault-Tolerant Comput., Newton, Mass, New York, N. Y. (1972), pp. 170–175.
M. Servit, “Hazard correction in asynchronous sequential circuits using inertial delay elements,” IEEE Trans. Comput.,22, No. 10, 1041–1042 (1973).
S. Singh, “On delayed-input asynchronous sequential circuits,” IEEE Trans. Comput.,20, No. 5, 500–503 (1971).
J. R. Smith and C. H. Roth, “Analysis and synthesis of asynchronous sequential networks using edge-sensitive flip-flops,” IEEE Trans. Comput.,20, No. 8, 847–855 (1971).
R. J. Smith, “Generation of internal state assignments for large asynchronous sequential machines,” IEEE Trans. Comput.,23, No. 9, 924–932 (1974).
J. Sosnowski, “Determination of excitation functions of elementary automata,” Arch. Automat. Telemech.,17, No. 1, 3–19 (1972).
Chung-Jen Tan, “State assignments for asynchronous sequential machines,” Proc. 7th Annual Allerton Conf. Circuit and Syst. Theory, Monticello, Ill. (New York, N. Y.), s. a., 661 (1969).
Chung-Jen Tan, “State assignments for asynchronous sequential machines,” IEEE Trans. Comput.,20, No. 4, 382–391 (1971).
Yoshihiro Tohma, Yasuyoshi Ohyama, and Ryozo Sakai, “Realization of fail-safe sequential machines by using a k-out-of-n code,” IEEE Trans. Comput.,20, No. 11, 1270–1275 (1971).
S. H. Unger, Asynchronous Sequential Switching Circuits, Wiley, New York (1969).
S. H. Unger, “Asynchronous sequential switching circuits with unrestricted input changes,” IEEE Conf. Rec. 11th Annual Symp. Switch. and Automata Theory, Santa Monica, Calif., 1970, New York, N. Y. (1970), pp. 114–121.
I. Vizirev, “Realization of asynchronous finite automata with multiple-input changes by transforming the flow table,” Proceed. Inter. Seminar on Applied Aspects of Automata Theory, Varna, 1971, Vol. 2, Varna (1971), pp. 255–262.
E. A. Yakubaitis, “A cyclic model of a finite automaton,” Proc. IFAC 5th World Congr., Part 4, S. 1, s. a., 39-4/1-39-4/6 (1972).
Literature cited
V. P. Aleksandrov, “Pulse noise-immunity of logic element circuits,” Avtomat. Vychisl. Tekh., No. 5, 65–70 (1971).
V. P. Aleksandrov, “Time analysis of races in asynchronous logic automata,” Izv. Vyssh. Uchebn. Zaved., Priborostr.,15, No. 8, 62–67 (1972).
N. N. Bochanova, “Analysis of dynamic mode of finite automata,” in: Reliability of Control Systems, Naukova Dumka, Kiev (1973), pp. 78–82.
T. M. Vorob'eva, K. A. Iyudu, and V. N. Kruglov, “Dynamic characteristics of logic networks,” Avtomat. Telemekh., No. 3, 172–177 (1971).
M. A. Gavrilov, V. M. Ostiany, and A. I. Potekhin, “Reliability of discrete systems,” in: Teor. Veroyatn. Mat. Stat., Teor. Kibernetika. 1969(Itogi Nauki. VINITI AN SSSR), Moscow (1970), pp. 7–104.
É. A. Dobracheva, “One-cycle attenuation in asynchronous circuits,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 3, 122–128 (1973).
Ya. N. Kobrinskii and N. N. Zubov, “Ensuring stability in potential logic circuits. I,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 6, 149–159 (1972).
Ya. N. Kobrinskii and N. N. Zubov, “Ensuring the stability of transitions in potential logic Circuits. II,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 2, 97–105 (1974).
V. I. Levin, “Infinite-valued logic and transient processes in finite automata,” Avtomat. Vychisl. Tekh., No. 6, 1–9 (1972).
V. I. Levin, “Minimization of representation of transient processes in asynchronous automata,” Avtom. Vychisl. Tekh., No. 6, 9–12 (1973).
V. I. Levin, “Transient processes in typical logic circuits,” Avtomat. Vychisl. Tekh., No. 6, 13–14 (1973).
V. I. Levin, “Decomposition of transient processes in finite automata,” Avtomat. Vychisl. Tekh., No. 6, 19–24 (1973).
V. I. Levin, “Transient processes in discrete devices,” Upr. Sistemy Mashiny, No. 5, 119–122 (1973).
V. I. Levin, “Analysis of transient processes in combinational circuits,” Elektron. Inf. Kybern.,9, No. 6, 355–364 (1973).
V. I. Levin, “Transient processes in multiinput logic elements,” in: Theory of Finite Automata and Its Applications, No. 2, Zinatne, Riga (1973), pp. 31–45.
V. I. Levin, “Transient processes in simplest asynchronous automata with memory,” Avtomat. Vychisl. Tekh., No. 2, 24–28 (1974).
V. I. Levin, “Analysis of switching dynamics of automata with memory,” Avtomat. Vychisl. Tekh., No. 3, 15–23 (1974).
V. I. Levin, “Equations in infinite-valued logic and transient processes in finite automata,” Avtomat. Vychisl. Tekh., No. 5, 12–17 (1974).
V. I. Levin, “Analysis of asynchronous automata,” in: Theory of Finite Automata and Its Applications, No. 4, Zinatne, Riga (1974), pp. 68–77.
V. I. Levin, “Analysis of mode of generation in asynchronous automata,” Avtomat. Vychisl. Tekh., No. 4, 21–23 (1974).
V. I. Levin, “Equations in infinite-valued logic with deviating arguments,” Avtomat. Vychisl. Tekh., No. 1, 17–20 (1975).
V. I. Levin, “Transient processes in combinational circuits with delayed signal edges,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 2, 118–127 (1975).
V. I. Levin, Introduction to Dynamic Theory of Finite Automata [in Russian], Zinatne, Riga (1975).
R. Miller, Theory of Switching Circuits, Vol. I, Combinational Circuits [Russian translation], Nauka, Moscow (1970); Vol. II, Sequential Circuits and Machines, Nauka, Moscow (1971).
M. G. Millerova, “Time analysis of asynchronous logic networks,” Avtomat. Telemekh., No. 6, 162–165 (1973).
M. G. Millerova, “A method of transition from logic schemes of algorithms to an asynchronous logic network,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 2, 105–109 (1973).
M. G. Millerova, “Structural transformation and time analysis of asynchronous automata,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 2, 128–134 (1975).
W. Müller, “Probabilistic method of analysis of operation of dynamic automata,” Tr. Uchebn. In-tov Svyazi, Ministry of Communications of the USSR, No. 59, 91–96, Leningrad (1972).
V. N. Roginskii, “Dynamic automata and Boolean time functions. I,” Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 2, 109–118 (1970); II. Izv. Akad. Nauk SSSR, Tekh. Kibernetika, No. 3, 86–98 (1970).
V. N. Roginskii, Foundations of Discrete Automation (Statics and Dynamics of Discrete Automata) [in Russian], Svyaz', Moscow (1975).
V. N. Roginskii and W. Müller, “A dynamic automaton as a new model of relay devices,” Izv. Vyssh. Uchebn. Zaved., Elektromekh., No. 5, 479–488 (1973).
Yu. L. Tomfel'd, “Modes of operation of feedback loop of asynchronous logic network,” Avtomat. Telemekh., No. 3, 89–96 (1973).
É. A. Yakubaitis, Logic Automata and Micromodules [in Russian], Zinatne, Riga (1975).
D. Bochmann, “Dynamic operations in switching algebra,” Nachrichtentechnik, Vol. 1,21, No. 6, 227–229 (1971); Vol. 2,21, No. 8, 282–283 (1971); Vol. 3,22, No. 6, 189–191 (1972).
D. Bochmann, “Mathematical description of time processes in switching networks,” ZKI-Information,2, 65–70 (1973).
D. Bochmann, “Mathematical description of time processes in switching networks,” Nachrichtentechnik-Elektronik,23, No. 9, 325–327 (1973).
D. Bochmann, “Concept and methods of function optimization,” ZKI-Informationen, 1, 7–11 (1974).
D. Bochmann, “Binary signals and systems,” Nachrichtentechnik-Elektronik,25, No. 5, 166–171 (1975).
D. Bochmann, Introduction to Structural Automata Theory [in German], Technik Verlag, Berlin (1975);
D. Bochmann and M. Kieser, “Experience with a dialog-capable language for analysis of logic switching circuits,” Nachrichtentechnik-Elektronik,23, No. 4, 132 (1973).
W. Müller, “The dynamic automaton as a model for analysis of digital networks,” INT-Information, No. 1, 3–15 (1971).
W. Müller, “Analysis of transient processes in digital networks with the aid of probability functions,” Nachrichtentechnik,22, No. 2, 33–36 (1972).
W. Müller and V. N. Roginskii (W. N. Roginskiy), “The dynamic automaton as a new model for analyzing the transient performance in digital circuits,” Nachrichtentechnik,22, No. 6, 184–188 (1972).
J. Sifakis, “Study of Boolean time algebra,” C. R. Acad. Sci. Paris,275, No. 25, A1343-A1346 (1972).
J. Sifakis, “Time models of logic systems,” Ph. D. Thesis Univ. Sci. Med. Grenoble (1974).
A. Thayse, “Boolean differential calculus,” Philips Res. Rept.,26, 229–249 (1971).
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Translated from Itogi Nauki i Tekhniki. Teoriya Veroyatnostei, Matematicheskaya Statistika, Teoreticheskaya Kibernetika, Vol. 14, pp. 81–122, 1977.
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Potekhin, A.I., Roginskii, V.N. Dynamics of discrete automata. J Math Sci 13, 505–532 (1980). https://doi.org/10.1007/BF01673629
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DOI: https://doi.org/10.1007/BF01673629