Skip to main content
SpringerLink
Log in

DSP design tool requirements for embedded systems: A telecommunications industrial perspective

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

This paper describes the trends in DSP (Digital Signal Processing) for telecommunications design at Bell Northern Research (BNR)1 and the tools needed to address them. The paper is in three parts: First, we present the results of a three month survey of DSP design practices at BNR. We briefly describe the characteristics of the designs, as well as the DSP design tools used. However, the emphasis is on the main bottlenecks in the design process, and the tools required to address them in the future. Then, we present a proposal for a next generation DSP design environment for telecommunication applications, based on the survey results. Particular emphasis will be given to code generation, system-level simulation, and behavioral synthesis, the three most requested design tools. Finally, we provide a description of FlexWare, an embedded software development system which is being developed internally. This system addresses one important aspect of this next generation environment, namely design tools for application-specific instruction-set processors (ASIP). FlexWare is composed of two main components: CodeSyn, a retargetable microcode synthesis system; and Insulin, a VHDL-based instruction set simulation system.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. G. Ward, “Logic Synthesis at BNR: A Synful Alternative,”Proc. of the Canadian Conference on VLSI, Ottawa, Sept. 1990.

  2. P.G. Paulin and J.P. Knight, “High-Level Synthesis Algorithms,”IEEE Design & Test Magazine, Oct. 1989, pp. 18–31.

  3. P.G. Paulin, “Global Scheduling and Allocation Algorithms in the HAL System,” from R. Camposano and W. Wolf, eds.,High-Level VLSI Synthesis, Chapter 11, Kluwer Academic Publishers, 1991, pp. 283–306.

  4. H. DeMan et al., “Architecture-Driven Synthesis Techniques for VLSI Implementation of DSP Algorithms,”Proceedings of the IEEE, Vol. 78, 1990, pp. 319–335.

    Article  Google Scholar 

  5. C.M. Chu, M. Potkonjac, M. Thaler and J. Rabaey, “Hyper: An Interactive Synthesis Environment for High-Performance Real-Time Applications,”Proc. of the International Conference on Computer Design (ICCD), Cambridge, October 1989, pp. 432–435.

  6. P.G. Paulin, “DSP Design Tool Requirements for the Nineties: An Industrial Perspective,”Proc. of the Sixth International High-Level Synthesis Workshop, Laguna Niguel, California, Nov. 1992.

  7. M.C. McFarland, A.C. Parker and R. Camposano, “The High-Level Synthesis of Digital Systems,”Proc. of IEEE, Vol. 78, 1990, pp. 301–318.

    Article  Google Scholar 

  8. CCITT recommendation Z. 100, SDL, 1989.

  9. P. Hilfinger, “A High-Level Language and Silicon Compiler for Digital Signal Processing,” IEEE Design & Test Magazine, Dec. 1988.

  10. J. Nestor et al., “MIES: A Microarchitecture Design Tool,”Proceedings of 22nd Workshop on Microprogramming and Microarchitecture, Dublin, Ireland, Aug. 1989.

  11. J. Nestor et al., “Visual Register-Transfer Description of VLSI Microarchitectures,”IEEE Transactions on VLSI Systems, Vol. 1, 1993, pp. 72–75.

    Article  Google Scholar 

  12. R. Woudsma et al., “VHDL Modelling of Reconfigurable DSP Architectures,”Proc. of IEEE Benelux & ProRISC Workshop on CSSP, Houthalen, Belgium, April 1992.

  13. “IEEE Standard VHDL LRM,” IEEE Std 1076–1987.

  14. K. Rimey and P. Hilfinger, “A Compiler for Application-Specific Signal Processors,” in R. W. Broderson and H. S. Moscovitz, eds.,VLSI Signal Processing III, New York: IEEE Press, 1988, pp. 341–351.

    Google Scholar 

  15. M. Breternitz and J.P. Shen, “Architecture Synthesis of High-Performance Application-Specific Processors,”Proceedings of the 27th Design Automation Conference (DAC), June 1990, pp. 542–548.

  16. M.J. Flynn and R.I. Winner, “ASIC Microprocessors,”Proceedings of 22nd Workshop on Microprogramming and Microarchitecture, Dublin, Ireland, Aug. 1989, pp. 237–243.

  17. G. Goossens, F. Catthoor, D. Laneer and H. De Man, “Integration of Signal Processing Systems on Heterogeneous IC Architectures,”Proc. of Sixth International Workshop on High-Level Synthesis, Laguana Niguel, CA, Nov. 1992.

  18. M. Horowitz and K. Keutzer, “Hardware-Software Co-Design,”Proc. of the Synthesis and Simulation Meeting and International Interchange (SASIMI), Nara, Japan, Oct. 1993, pp. 5–13.

  19. H. Mulder and R.J. Portier, “Cost-Effective Design of Application-Specific VLIW Processors Using the SCARCE Framework,”Proceedings of 22nd Workshop on Microprogramming and Microarchitecture, Dublin, Ireland, Aug. 1989, pp. 35–42.

  20. C. Shung, R. Jain, K. Rimey, E. Wang, M. Srivastava, B. Richards, E. Lettang, S. Azim, L. Thon, P. Hilfinger, J. Rabaey and R. Broderson, “An Integrated CAD System for Algorithmic-Specific IC Design,”IEEE Transactions on Computer-Aided Design, Vol. 10, 1991, pp. 447–463.

    Article  Google Scholar 

  21. gnA. Wolfe and J.P. Shen, “Flexible Processors: A Promising Application-Specific Processor Design Approach,”Proceedings of 21st Workshop on Microprogramming and Microarchitecture, San Diego, CA, Nov. 1988, pp. 30–39.

  22. D.W. Knapp, “An Interactive Tool for Register-Level Structure Optimization,”Proc. of the 26th Design Automation Conference (DAC), June 1989, pp. 598–601.

  23. I-J. Huang and A.M. Despain, “High-Level Synthesis of Pipelined Instruction-Set Processors and Back-End Compilers,”Proc. of the 29th ACM/IEEE Design Automation Conference, Anaheim, California, June 1992, pp. 135–140.

  24. D. Harel et al, “Statecharts: A Working Environment for the Development of Complex Reactive Systems,”IEEE Trans. on Software Engineering, Vol. 16, 1990, pp. 403–413.

    Article  Google Scholar 

  25. J. Buck, S. Ha, E.A. Lee and D.G. Messerschmitt, “Ptolemy: a Platform for Heterogeneous Simulation and Prototyping,”Proc. of 1991 European Simulation Conference, Copenhagen, Denmark, June 1991.

  26. D.W. Franke and M.K. Purvis, “Design Automation Technology for CoDesign: Status and Directions,”Proc. of Intl. Symposium on Circuits and Systems, San Diego, May 1992, pp. 2669–2671.

  27. Contributed Papers from Special Issue on Firmware Engineering,IEEE Software Magazine, Vol. 3, No. 4, July 1986.

  28. K. Rimey and P. Hilfinger, “Lazy Data Routing and Greedy Scheduling for Application-Specific Signal Processors,”Proc. of the 21st Annual Workshop on Microprogramming and Microarchitecture, San Diego, Nov. 1988, pp. 111–115.

  29. S.R. Vegdahl, “Microcode Optimization: Examples and Approaches,”IEEE Software Magazine, Vol. 3, No. 4, July 1986.

  30. C.A. Papachristou and S. B. Gambhir, “Microcontrol Architectures with Sequencing Firmware and Modular Microcode Development Tools,” North-Holland,Microprocessing and Microprogramming 29, 1990/91, pp. 303–328.

  31. T. Baba, H. Minakawa and K. Okuda, “A Visual Microprogramming System,” ACM, 1987, pp. 23–30.

  32. T. Krol, J.V. Meerburgen, C. Niessen, W. Smits and J. Huisken, “The Sprite Input Language: An Intermediate Format for High-Level Synthesis,”Proc. of European Conference on Design Automation (EDAC), Brussels, Belgium, March 1992.

  33. D.W. Knapp and A.C. Parker, “A Unified Representation for Design Information,”Proc. CHDL-85, 1985.

  34. A.V. Aho and S.C. Johnson, “Optimal Code Generation for Expression Trees,” Journal of the Association for Computing Machinery, Vol. 23, 1976, pp. 488–501.

    Article  MathSciNet  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. SGS-Thomson Microelectronics, 850, rue Jean Monnet, BP 16, 38921, Crolles, France

    Pierre G. Paulin

  2. TIMA Lab, Institut National Polytechnique de Grenoble, 46, Av. Felix Viallet, 38031, Grenoble, France

    Clifford Liem

  3. Bell-Northern Research, Stn. “C”, PO. Box 3511, K1Y 4H7, Ottawa, Canada

    Trevor C. May & Shailesh Sutarwala

Authors
  1. Pierre G. Paulin
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Clifford Liem
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Trevor C. May
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Shailesh Sutarwala
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Paulin, P.G., Liem, C., May, T.C. et al. DSP design tool requirements for embedded systems: A telecommunications industrial perspective. Journal of VLSI Signal Processing 9, 23–47 (1995). https://doi.org/10.1007/BF02406469

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF02406469

Keywords

Search

Navigation