Anneal behavior of defects in lon-lmplanted GaAs diodes

Abstract

Doping of semiconductors by implantation of high-energy ions creates lattice damage which in general must be removed by annealing to form good qualityp-n junctions. Implantation of zinc or cadmium ions inton-type gallium arsenide substrates held at 400°C produces ap-n junction after the samples are annealed at elevated temperature (≥500°C for zinc, ≥600°C for cadmium). However, the resulting junctions are not abrupt; they contain a semiinsulating (I) layer and have ap-i-n structure. The thickness of the semiinsulating layer changes with annealing. For example, an implant of 1.3×10¹⁵ per sq cm, 20 kv, Zn⁺ ions produced a junction with an I layer of 28 μ thickness after annealing for 10 min at 600°C. An identically implanted sample, annealed for 10 min at 900°C, had an I layer thickness of 120 μ. A similar increase in I layer thickness with annealing was observed for samples implanted with 20 kv Cd⁺ ions at 400°C. Implantation of Zn⁺ and Cd⁺ ions into GaAs substrates held at room temperature produced junctions with much thinner I layers after annealing than those observed for the 400°C implants. The formation of the semiinsulating layer in the junction and its subsequent variation of thickness with annealing are attributed to deep diffusion of defects during the implantation or subsequent anneal, which produces compensation to the depth where the concentration of defects equals the substrate impurity concentration. The compensating centers are thought to be arsenic vacancy-substrate dopant atom complexes.