Skip to main content
SpringerLink
Log in

Area–Energy–Error Optimized Faithful Multiplier for Digital Signal Processing

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

Approximate computing is a striking approach to design area-efficient low-power datapath units for fault buoyant applications. This brief presents the design of a novel 4: 2 approximate compressor that generates no error in the carry signal. The proposed compressor is employed for partial product (PP) compression in two variants of Dadda multiplier to see its effectiveness in error-resilient image and signal processing applications. In the targeted multipliers, the approximate 4:2 compressor is used in the least n PP columns, while the exact counterpart is used in the remaining most significant columns, and hence the maximum error is precisely maintained within 2n. PP compression is performed in stages using the Wallace approach, and the final two rows of sum and carry signals are added using a ripple carry adder in the basic design. In the proposed multiplier design-2, we do not generate sum bits in the approximate part. However, the proposed error-tolerant compressor is used in appropriate columns to propagate carry to the least significant column in the exact part. Performance evaluations using Cadence Encounter with 90 nm application specific integrated circuit technology revealed that the proposed-full width (P-FW) and the proposed-truncated (P-Trun) approximate multipliers demonstrate 22.7% and 32.4% power-delay product reduction compared to the standard multiplier. Implementations of the proposed multipliers in signal and image processing applications revealed superior performance in terms of accuracy compared to prior similar approximate designs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig.7
Fig.8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

Data availability

ECG Data analyzed for the research work is taken from https://physionet.org/content/ecgiddb/1.0.0/.

References

  1. A. Afzali-Kusha, O. Akbari, M. Kamal, M. Pedram, Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Trans. Very Large Scale Integr. Syst. 25(4), 1352–1361 (2017)

    Article  Google Scholar 

  2. A. Al-Haj, A hybrid digital image watermarking algorithm, IEEE Inn. Info.Tech, pp.690–694 (2008)

  3. S. Amra, A. Kaur, A secure and robust image watermarking system using wavelet domain, IEEE Int. Con. Cloud. Comput. Data. sci. Eng (2017)

  4. NV Arora, Anew 16-bit high speed and variable stage carry skip adder. IEEE Int. Con. Comput. Intell. Com. tec (2017)

  5. P.R. Cappello, K. Steiglitz, A VLSI layout for a pipe-lined Dadda multiplier. ACM Trans. Comput. Syst. 1, 157–174 (1983)

    Article  Google Scholar 

  6. C.H. Chang, J. Gu, M. Zhang, Ultra low-voltage, low power CMOS 4–2 and 5–2 compressors for fast arithmetic circuits. IEEE Trans. Circuit Syst. 51(4), 1997–1985 (2004)

    Article  Google Scholar 

  7. K.J. Cho, K.C. Lee, J.G. Chung, K.K. Parhi, Design of low error fixed-width modified boot multiplier. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(5), 522–531 (2004)

    Article  Google Scholar 

  8. A. Dalloo, A. Najafi, A. Garcia-Ortiz, Systematic design of an approximate adder: the optimized lower part constant—OR adder. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(8), 1595–1599 (2018)

    Article  Google Scholar 

  9. D. Dwivedi, K.M. Reddy, Y.B. Nithin Kumar, M.H. Vasantha, Design and analysis of multiplier using approximate 4–2 compressor. AEU- Int. J. Electron. Commun. 107, 89–97 (2019)

    Article  Google Scholar 

  10. P. Gnanambikai, K.N. Vijeyakumar, S. Kalaiselvi, Area-efficient parallel adder with faithful approximation for image and signal processing applications. Inst. Eng. Technol. 13(13), 2587–2594 (2019)

    Google Scholar 

  11. M. Ha, S. Lee, Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embedded Syst. Lett. 10(1), 6–9 (2018)

    Article  Google Scholar 

  12. J. Han, F. Lombardi, A. Momeni, P. Montuschi, Design and analysis of approximate compressors for multiplication. IEEE Trans. Comput. 64(4), 984–994 (2015)

    Article  MathSciNet  Google Scholar 

  13. https://physionet.org/content/ecgiddb/1.0.0/, 2014.

  14. R. Jothin, C. Vasanthanayaki, High performance significance approximation error tolerance adder for image processing applications. J. Electron. Test. 32(3), 3707–4383 (2016)

    Article  Google Scholar 

  15. R. Jothin, C. Vasanthanayaki, High speed energy efficient static segment adder for approximate computing applications. J. Electron. Test. 33(1), 125–132 (2017)

    Article  Google Scholar 

  16. R. Jothin, C. Vasanthanayaki, High performance error tolerance adders for image processing applications. IETE J. Res. 32(3), 377–383 (2018)

    Google Scholar 

  17. D. Karthik, S. Jayamani, High Speed energy efficient carry skip adder operating at different voltage supply. IEEE WiSPNET conference (2016).

  18. S. Kuang, J. Wang, Low-error configurable truncated multiplier for multiply-accumulate applications. Electron. Lett. 42(16), 904–905 (2006)

    Article  Google Scholar 

  19. Mahalakshmi R, Sasilatha T, A Power efficient carry save adder and modified carry save adder using CMOS technology. IEEE Int. Conf. Comput. Intell. Comput. Res. (2013)

  20. K. Manikanta, Manjunath, S. Sivanantham, K. Sivasankaran, V. Harikiran, Design and implementation of 16 x 16 modified booth multiplier. In International Conference on Green Engineering and Technologies. (2015).

  21. A.G. Naik, D. Pal, R. Pal, A. Saha, Novel CMOS multi- bit counter for speed-power optimization in multiplier design. AEU- Int. J. Electron. Commun. 95, 189–198 (2018)

    Article  Google Scholar 

  22. K. Pekmestzi, D. Soudris, K. Tsoumanis, S. Xydis, G. Zervakis, Hybrid approximate multiplier architectures for improved power-accuracy trade-offs. in IEEE/ACM International Symposium on Low Power Electronics and Design (2015).

  23. N. Petra, D. De. Caro, V. Garofalo, E. Napoli, A.G.M. Strollo, Design of fixed-width linear multipliers with linear compensation function. IEEE Trans. Circ. Syst. 58, 947–960 (2011)

    MathSciNet  Google Scholar 

  24. M. Pourormazd, R. Bahram, R. Bahman, Design and implementation of low power digital FIR filter based on low power multipliers and adders on xilinx FPGA. IEEE Int. Conf. Electron. Comput. Technol. 2, 18–22 (2011)

    Google Scholar 

  25. K.M. Priyadarshini, N.R. Kiran, N. Tejasri, T.C. Venkat Anish, Design of area and speed efficient square root carry select adder using fast adders. Int. J. Sci. Technol. Res. 3(6), 133–138 (2014)

    Google Scholar 

  26. B. Ram Kumar, M.K. Harish, Low-power and area–efficient carry select adder. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2(2), 371–375 (2012)

    Article  Google Scholar 

  27. D. Shi, Y.J. Yu, Design of linear phase fir filters with high probability of achieving minimum number of adders. IEEE Trans. Circ. Syst 58(1), 126–136 (2011)

    MathSciNet  MATH  Google Scholar 

  28. Silviu-Ioan Filip. “A robust and scalable implementation of the Parks-McClellan algorithm for designing FIR filters.” 2015. ffhal-01136005v1f.

  29. L. Van, C. Yang, Generalized low-error area-efficient fixed-width multipliers. IEEE Trans. Circ. Syst. 52(8), 1608–1619 (2005)

    Article  Google Scholar 

  30. S. Venkatachalam, H.J. Lee, S.-B. Ko, Power efficient approximate booth multiplier. IEEE Int. Sympos. Circuits Syst. (2018)

  31. K.N. VijeyaKumar, S. Elango, S. Kalaiselvi, VLSI implementation of high speed energy-efficient truncated multiplier. J. Circuits Syst. Comput. 27(5), 1850077 (2018)

    Article  Google Scholar 

  32. J.P. Wang, S.R. Kuang, S.C. Liang, High-accuracy fixed-width modified booth multipliers forlossy applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(1), 52–60 (2011)

    Article  Google Scholar 

  33. X. Wenbin, S.S. Sachin, H. Jiang, A simple yet efficient accuracy-configurable adder design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(6), 1112–1125 (2018)

    Article  Google Scholar 

  34. N. Zhu, W.L. Goh, W. Zhang, Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(8), 1225–1229 (2010)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Tamil Nadu, India

    Kalaiselvi Sundaram, Vijeyakumar Krishnasamy Natarajan, Kousalya Manoharan, Ramya Ramasamy & Sriram Kumar

  2. TNEB, Chennai, Tamil Nadu, India

    Nagarajan Shanmugam

Authors
  1. Kalaiselvi Sundaram
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vijeyakumar Krishnasamy Natarajan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Nagarajan Shanmugam
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Kousalya Manoharan
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Ramya Ramasamy
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Sriram Kumar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kalaiselvi Sundaram.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sundaram, K., Natarajan, V.K., Shanmugam, N. et al. Area–Energy–Error Optimized Faithful Multiplier for Digital Signal Processing. Circuits Syst Signal Process 40, 6224–6241 (2021). https://doi.org/10.1007/s00034-021-01765-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-021-01765-y

Keywords

Search

Navigation