Abstract
Scheduling of a semiconductor wafer fabrication system (SWFS) is complicated due to its re-entrant product flow, high uncertainties in operations, and rapidly changing products and technologies; thus dispatching rules have been widely used for real-time scheduling because they can provide a very quick and pretty good solution. However, deciding how to select appropriate rules is very difficult and seldom tackled. This paper describes an approach into the evaluation and optimization of dispatching rules by integrating the simulation and response surface methodology (RSM). In order to implement the proposed approach, a dynamic bottleneck dispatching (DBD) policy is designed, in which bottlenecks are detected in a timely way and adaptive dispatching decisions are made according to the real-time conditions. In addition, two case studies are carried out to demonstrate the approach. One case compares DBD to regular rules, such as CR + FIFO, EDD, SRPT, SPT, SPNB and Justice, a bottleneck dispatching method. Simulation results show that the DBD policy is superior to the other six methods. In another case study, the parameters of DBD are optimized by RSM and desirability function, and the result proves that the optimized DBD method can get even better performance.
Similar content being viewed by others
References
Geiger C, Kempf K, Uzsoy R (1997) A tabu search approach to scheduling an automated wet etch station. J Manuf Syst 16(2):102–116
Kim YD, Shim SO, Choi B, Hwang H (2003) Simplification methods for accelerating simulation-based real-time scheduling in a semiconductor wafer fabrication facility. IEEE Trans Semicond Manuf 16(2):290–298
Kumar PR (1994) Scheduling semiconductor manufacturing plants. IEEE Control Systems Magazine IEEE Control Syst Mag 14(6):33–40
Li S, Tang T, Collins, DW (1996) Minimum inventory variability schedule with applications in semiconductor fabrication. IEEE Trans Semicond Manuf 9(1):145–149
Lu SH, Ramaswamy D, Kumar PR (1994) Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants. IEEE Trans Semicond Manuf 7(3):374–388
Hung YF, Chen IR (1998) A simulation study of dispatch rules for reducing flow times in semiconductor wafer fabrication. Prod Plan Control 9(7):714–722
Tyan JC, Chen JC, Wang FK (2002) Development of a state-dependent dispatch rule using theory of constraints in near-real-world wafer fabrication. Prod Plan Control 13(3):253–261
Wu MC, Huang YL, Chang YC, Yang KF (2006) Dispatching in semiconductor fabs with machine-dedication features. Int J Adv Manuf Technol 28(9):978–984
Li L, Qiao F, Jiang H, Wu Q (2004) The research on dispatching rule for improving on-time delivery for semiconductor wafer fab, 8th International Conference on Control, Automation, Robotics and Vision (ICARCV). 494–498
Hsieh S, Hou KC (2006) Production-flow-value-based job dispatching method for semiconductor manufacturing. Int J Adv Manuf Technol 30(7–8):727–737
Lacomme P, Moukrim A, Tchernev N (2005) Simultaneous job input sequencing and vehicle dispatching in a single-vehicle automated guided vehicle system: a heuristic branch-and-bound approach coupled with a discrete events simulation model. Int J Prod Res 43(9):1911–1942
Kumar S, Nottestad DA (2006) Integrated simulation application design for short-term production scheduling. IIE Trans 38(9):737–748
Jeong SJ, Lim SJ, Kim KS (2006) Hybrid approach to production scheduling using genetic algorithm and simulation. Int J Adv Manuf Technol 28(1–2):129–136
Law AM, Kelton WD (1991) Simulation Modeling and Analysis. McGraw-Hill, New York
Banks J, John SC, Barry LN, David MN (2001) Discrete-Event Simulation. Prentice-Hall, Upper Saddle River
Yang J, Chang TS (1998) Multi objective scheduling for IC sort and test with a simulation testbed. IEEE Trans Semicond Manuf 11(2):304–315
Tyan JC, Du TC, Chen JC, Chang IrHIH (2004) Multiple response optimization in a fully automated FAB: An integrated tool and vehicle dispatching strategy. Comput Ind Eng 46(1):121–139
Sourirajan K, Uzsoy R (2007) Hybrid decomposition heuristics for solving large-scale scheduling problems in semiconductor wafer fabrication. J Sched 10(1):41–65
Liu HR, Jiang ZB, Fung RYK (2007) The infrastructure of the timed EOPNs-based multiple-objective real-time scheduling system for 300 mm wafer fab. Int J Prod Res 45(21):5017–5056
Dabbas RM, Fowler JW (2003) A new scheduling approach using combined dispatching criteria in wafer fabs. IEEE Trans Semicond Manuf 16(3):501–510
Box GEP, Wilson KB (1951) On the experimental attainment of optimum conditions. J R Stat Soc 13(1):1–45
Derringer GC, Suich R (1980) Simultaneous optimization of several response variables. J Qual Technol 12:214–219
Glassey CR, Resende MGC (1988) Closed loop job release control for VLSI circuit manufacturing. IEEE Trans Semicond Manuf 1(3):36–46
Wein LM (1988) Scheduling semiconductor wafer fabrication. IEEE Trans Semicond Manuf 1(3):115–130
Chiang TC, Huang AC, Fu LC (2006) Modeling, scheduling, and performance evaluation for wafer fabrication: A queueing colored Petri-net and GA-aased approach. IEEE Trans Autom Sci Eng 3(3):330–337
Jiang ZB, Zuo MJ, Tu YL, Fung RYK (1999) Object-oriented Petri nets with changeable structure (OPNs-CS) for production system modeling. Int J Adv Manuf Technol 15(6):443–459
Jiang ZB, Zuo MJ, Fung RYK, Tu YL (2000) Performance modeling of complexdynamic production system by temporized object-oriented Petri nets with changeable structure (TOPNs-CS) (TOPNs-CS). Int J Adv Manuf Technol 16(7):521–536
Jiang ZB, Fung RYK (2003) An adaptive agile manufacturing control infrastructure based on TOPNs-CS modeling. Int J Adv Manuf Technol 22(3–4):191–215
Nakata T, Matsui K, Miyake Y, Nishioka K (1999) Dynamic bottleneck control in wide variety production factory. IEEE Trans Semicond Manuf 12(3):273–280
Liu HR, Fung RYK, Jiang ZB (2005) Modeling of semiconductor wafer fabrication systems by extended object-oriented petri nets. Int J Prod Res 43(3):471–495
Liu HR, Jiang ZB, Fung RYK (2005) Modeling of the large-scale complex re-entrant manufacturing systems by extended object-oriented petri nets. Int J Adv Manuf Technol 27(1–2):190–204
NIST/SEMATECH. NIST/SEMATECH e-Handbook of Statistical Methods, Available online at:http://www.itl.nist.gov/div898/handbook
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Zhang, H., Jiang, Z. & Guo, C. Simulation-based optimization of dispatching rules for semiconductor wafer fabrication system scheduling by the response surface methodology. Int J Adv Manuf Technol 41, 110–121 (2009). https://doi.org/10.1007/s00170-008-1462-0
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00170-008-1462-0