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Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

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Abstract

A charge plasma technique based dopingless (DL) accumulation mode (AM) junctionless (JL) cylindrical surrounding gate (CSG) MOSFET has been proposed and extensively investigated. Proposed device has no physical junction at source to channel and channel to drain interface. The complete silicon pillar has been considered as undoped. The high free electron density or induced N+ region is designed by keeping the work function of source/drain metal contacts lower than the work function of undoped silicon. Thus, its fabrication complexity is drastically reduced by curbing the requirement of high temperature doping techniques. The electrical/analog characteristics for the proposed device has been extensively investigated using the numerical simulation and are compared with conventional junctionless cylindrical surrounding gate (JL-CSG) MOSFET with identical dimensions. For the numerical simulation purpose ATLAS-3D device simulator is used. The results show that the proposed device is more short channel immune to conventional JL-CSG MOSFET and suitable for faster switching applications due to higher I ON/I OFF ratio.

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Acknowledgements

One of the authors, Mr. Nitin Trivedi, is grateful to CSIR for providing financial assistance to carry out this research work. Authors are also grateful to the Director, Maharaja Agrasen Institute of Technology, for providing the facilities to carryout this research work.

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Authors and Affiliations

  1. Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi, 110021, India

    Nitin Trivedi, Manoj Kumar & Mridula Gupta

  2. Department of Physics, Motilal Nehru College, University of Delhi, New Delhi, 110021, India

    Subhasis Haldar

  3. Department of Electrical and Electronics Engineering, Maharaja Agrasen Institute of Technology, New Delhi, 110086, India

    S. S. Deswal

  4. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi, 110086, India

    R. S. Gupta

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  1. Nitin Trivedi
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  2. Manoj Kumar
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  3. Subhasis Haldar
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  4. S. S. Deswal
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  5. Mridula Gupta
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  6. R. S. Gupta
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Correspondence to Nitin Trivedi.

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Trivedi, N., Kumar, M., Haldar, S. et al. Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement. Appl. Phys. A 123, 564 (2017). https://doi.org/10.1007/s00339-017-1176-y

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  • DOI: https://doi.org/10.1007/s00339-017-1176-y

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