Skip to main content
SpringerLink
Log in

Interlayer cooling potential in vertically integrated packages

  • Technical Paper
  • Published:
Microsystem Technologies Aims and scope Submit manuscript

Abstract

The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters ≤200 μm. An experimental investigation with uniform and double-side heat flux at Reynolds numbers ≤1,000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 μm and fluid structure heights of 100–200 μm. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 μm interconnect pitch to <100 W/cm2 at 4 cm2. From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25
Fig. 26
Fig. 27
Fig. 28
Fig. 29
Fig. 30

Similar content being viewed by others

Abbreviations

TV-px-hy :

TV: test vehicle with x: interconnect pitch (μm) y: structure height (μm)

f :

area fill factor

s :

chip size (mm)

a :

length of heat-transfer area (mm)

b :

width of heat-transfer area (mm)

t :

silicon-base thickness (μm)

w c :

channel width (μm)

h c :

channel height (μm)

l c :

channel length (mm)

x :

position on chip in flow direction (mm)

d p :

heat-transfer structure diameter (μm)

d h :

hydraulic diameter [2 h c *w c /(h c  + w c )] (μm)

p :

pitch (μm)

S T :

transverse pin separation in a column (μm)

S L :

longitudinal distance between pin columns (μm)

N T :

number of pins in a transversal column

N L :

longitudinal number of pin columns

AR c :

aspect ratio of microchannel (h c /w c )

A t :

total wetted surface area (μm2)

A heater :

projected heater area (μm2)

P fin :

pin-fin perimeter (μm)

A fin :

pin-fin cross-sectional area (μm2)

η f :

fin efficiency

ΔP :

pressure drop (Pa)

\( \dot{V} \) :

volumetric flow rate (l/min)

\( \bar{v} \) :

average velocity (m/s)

v max :

mean velocity at minimal cross-section (m/s)

k :

thermal conductivity [W/(mK)]

η :

dynamic viscosity (Pa s)

ν :

kinematic viscosity (m2/s)

c p :

heat capacity [J/(kg*K)]

ρ :

density (kg/m3)

T in :

coolant inlet temperature (°C)

T out :

coolant outlet temperature (°C)

T surface :

chip back-side temperature (°C)

T j :

junction temperature (°C)

T jmax :

maximal junction temperature (°C)

T jcenter :

central junction temperature (°C)

ΔT j-in :

T j – T in (K)

ΔT jmax-in :

T jmax – T in (K)

ΔT cond :

T j – T surface (K)

ΔT conv :

convective temperature gradient (K)

ΔT heat :

T in – T out (K)

P pumping :

pumping power (W)

\( \dot{Q} \) :

heat flow (W)

\( \dot{q} \) :

heat flux (W/cm2)

h :

heat-transfer coefficient [(W/m2 K)]

R th :

thermal resistance (K mm2/W)

R cond :

conductive R th (K mm2/W)

R conv :

convective R th (K mm2/W)

R heat :

effective R th representing ΔT heat (K mm2/W)

R si :

R th of silicon base (K mm2/W)

R b :

R th of wiring levels (K mm2/W)

R TIM :

R th of thermal interface (K mm2/W)

R cp :

R th of cold plate (K mm2/W)

f r :

friction factor

Re :

Reynolds number (d h v max/ν)

Nu :

Nusselt number (d h h/k fluid)

a n :

coefficients

τ :

time constant

References

  • Andry P, Tsang C, Sprogis E, Patel C, Wright S, Webb B (2006) A CMOS-compatible process for fabricating electrical through-vias in silicon. In: Proceedings of electronic components and technology conference, pp 831–837

  • Bernstein K, Andry P, Cann J, Emma P, Greenberg D, Haensch W et al (2007) Interconnects in the third dimension: design challenges for 3D ICs. In: Proceedings of design automation conference, San Diego, pp 562–567

  • Brunschwiler T, Rothuizen H, Fabbri M, Kloter U, Michel B (2006) Direct liquid-jet impingement cooling with micron-sized nozzle array and distributed return architecture. In: Proceedings of ITHERM, San Diego, pp 196–203

  • Brunschwiler T, Michel B, Rothuizen H, Kloter U, Wunderle B, Oppermann H et al (2008) Forced convective interlayer cooling in vertically integrated packages. In: Proceedings of ITHERM, Orlando

  • Chen X, Toh K, Chai J (2002) Direct liquid cooling of a stacked multichip module. In: Proceedings of electronics packaging technology conference, pp 380–384

  • Colgan E, Furman B, Gaynes M, Graham W, LaBianca N, Magerlein J et al (2007) A practical implementation of silicon microchannel coolers for high power chips. IEEE Trans Components Packaging Technol 30:218–225. doi:10.1109/TCAPT.2007.897977

    Article  Google Scholar 

  • Havemann R, Hutchby J (2001) High-performance interconnects: an integration overview. Proc IEEE 89:586–601. doi:10.1109/5.929646

    Article  Google Scholar 

  • Incropera F (1999) Liquid cooling of electronic devices by single-phase convection, Chap 3. Wiley

  • Koo J, Im S, Jiang L, Goodson K (2005) Integrated microchannel cooling for three-dimensional electronic circuit architectures. J Heat Transfer 127:49–58. doi:10.1115/1.1839582

    Article  Google Scholar 

  • Kosar A, Peles Y (2007) Micro scale pin fin heat sinks—parametric performance evaluation study. IEEE Trans Components Packaging Technol 30:855–865. doi:10.1109/TCAPT.2007.906334

    Article  Google Scholar 

  • Lee H, Park S, Baek J, Lee J, Lee D, Oh S (2005) Thermal Characterization of high performance MCP with silicon spacer having low thermal impedance. In: Proceedings of 21st annual IEEE semiconductor thermal measurement and management symposium SEMI-THERM, pp 322–326

  • Linderman R, Brunschwiler T, Kloter U, Toy H, Michel B (2007) Hierarchical nested surface channels for reduced particle stacking and low-resistance thermal interfaces. In: Proceedings of 23rd annual IEEE semiconductor thermal measurement and management symposium SEMI-THERM, San Jose, CA, pp 87–94

  • Muzychka Y, Yovanovich M (2004) Laminar forced convection heat transfer in the combined entry region of non-circular ducts. Trans ASME 126:54–61. doi:10.1115/1.1643752

    Article  Google Scholar 

  • Peles Y, Kosar A, Mishra C, Kuo C, Schneider B (2005) Forced convective heat transfer across a pin fin micro heat sink. Int J Heat Mass Transfer 48:3615–3627. doi:10.1016/j.ijheatmasstransfer.2005.03.017

    Article  Google Scholar 

  • Prasher R, Dirner J, Chang J, Myers A, Chau D, He D, Prstic S (2007) Nusselt number and friction factor of staggered arrays of low aspect ratio micropin-fins under cross flow for water as fluid. J Heat Transfer 129:141–153. doi:10.1115/1.2402179

    Google Scholar 

  • Takahashi K, Taguchi Y, Tomisaka M, Yonemura H, Hoshino M, Ueno M et al (2004) Process integration of 3D chip stack with vertical interconnection. In: Proceedings of 54th IEEE electronic components and technology conference, vol 1, pp 601–609

  • Tuckerman D, Pease R (1981) High-performance heat sinking for VLSI. IEEE Electron Device Lett 2:126–129. doi:10.1109/EDL.1981.25367

    Article  Google Scholar 

  • Wong E, Lim S (2006) 3D floorplanning with thermal vias. In: Proceedings of design, automation and test, Europe, pp 878–883

Download references

Acknowledgments

We acknowledge Ryan Linderman, Reto Wälchli, Werner Escher, Martin Witzig, Ute Drechsler, Richard Stutz and Daniele Caimi for their technical contributions, and Paul Seidler for support.

Author information

Authors and Affiliations

  1. Zurich Research Laboratory, IBM Research GmbH, 8803, Rüschlikon, Switzerland

    T. Brunschwiler, B. Michel, H. Rothuizen & U. Kloter

  2. Fraunhofer Institute for Reliability and Microintegration, 13355, Berlin, Germany

    B. Wunderle & H. Oppermann

  3. Electrical Engineering, Technische Universität Berlin, 13355, Berlin, Germany

    H. Reichl

Authors
  1. T. Brunschwiler
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. B. Michel
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. H. Rothuizen
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. U. Kloter
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. B. Wunderle
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. H. Oppermann
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. H. Reichl
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to T. Brunschwiler.

Additional information

Based on “Forced Convective Interlayer Cooling in Vertically Integrated Packages”, T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Oppermann, and H. Reichl which appears in Proceedings of ITHERM 2008, Orlando FL. © [2008] IEEE.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Brunschwiler, T., Michel, B., Rothuizen, H. et al. Interlayer cooling potential in vertically integrated packages. Microsyst Technol 15, 57–74 (2009). https://doi.org/10.1007/s00542-008-0690-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00542-008-0690-4

Keywords

Search

Navigation