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A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

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Abstract

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0 µW/MHz versus 10.9 µW/MHz and more for 0.25 µm CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1 µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55 nW versus 0.84 nW in CSM and 0.94 nW in Wallace).

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Authors and Affiliations

  1. D-ITET, Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, Zurich, 8092, Switzerland

    Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin & Wolfgang Fichtner

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  1. Flavio Carbognani
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  2. Felix Buergin
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  3. Norbert Felber
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  4. Hubert Kaeslin
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  5. Wolfgang Fichtner
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Correspondence to Flavio Carbognani.

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Carbognani, F., Buergin, F., Felber, N. et al. A low-power transmission-gate-based 16-bit multiplier for digital hearing aids. Analog Integr Circ Sig Process 56, 5–12 (2008). https://doi.org/10.1007/s10470-007-9086-0

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  • DOI: https://doi.org/10.1007/s10470-007-9086-0

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