Abstract
As MOSFET scaling pushes channel lengths below 65 nm, device designs utilizing fully depleted silicon-on-insulator (SOI) technology and employing two or more gates are becoming increasingly attractive as a means to counteract short channel effects. The presence of multiple gates enhances the total control that the gate exercises on the channel region and the SOI technology allows for a significant reduction in the junction capacitance. In combination, these two factors result in devices that exhibit superior characteristics to the conventional planar MOSFET. This paper compares the variation in the switching performance of the three leading multi-gate MOSFET designs, namely the FinFET, TriGate, and Omega-gate. A 3-dimensional, commercial numerical device simulator is employed to investigate the device characteristics using a common set of material parameters, device physics models, and performance metrics. Examined initially are the short-channel effects including the subthreshold slope (S) and the drain-induced barrier lowering as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin’s body width and height, the oxide thickness, and channel doping. The investigation reveals that the Omega-gate MOSFET shows the best scaling characteristics at a particular device dimension with the TriGate device showing the least variation in characteristics as device dimensions vary.
Similar content being viewed by others
References
Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., & Hu, C. (2000). FinFET—A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices, 47(12), 2320–2325.
Chau, R., Doyle, B., & Datta, S. (2003). Silicon nano-transistors for logic applications. Physical Review Letters, 19(1–2), 1–5.
Doyle, B. S., Datta, S., & Chau, R. (2003). High performance fully-depleted Tri-gate CMOS transistors. IEEE Electron Device Letters, 24(4), 263–265.
Yang, F.-L., Chen, H.-Y., Chen, F.-C., Huang, C.-C., Chang, C.-Y., Chiu, H.-K., Lee, C.-C., Chen, C.-C., Huang, H.-T., Chen, C.-J., Tao, H.-J., Yeo, Y.-C., Liang, M.-S., & Hu, C. (2002). 25 nm CMOS Omega FETs. In IEDM Technical Digest (pp. 255–258).
Kim, D. H., et al. (2001). Single electron transistors with sidewall depletion gates on a silicon-on-insulator quantum wire. In Device Research Conference (pp. 133–134).
Colinge, J.-P. (2004). Novel gate concepts for MOS devices. In Proceedings of ESSDERC (pp. 45–49).
Fossum, J. G., Chowdhury, M. M., Trivedi, V. P., King, T. J., Choi, Y.-K., An, J., & Yu, B. (2003). Physical insights on design and modeling of nanoscale FinFETs. In IEDM Technical Digest (pp. 679–682).
Pei, G., Kedzierski, J., Oldiges, P., Iong, M., & Kan, E. C. C. (2002). FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Transactiions on Electron Devices, 49(8), 1411–1419.
Doyle, B., Boyanov, B., Datta, S., Doczy, M., Hare-land, S., Jin, B., Kavalieros, J., Linton, T., Rios, R., & Chau, R. (2003). Tri-gate fully depleted CMOS transistors: Fabrication, design and layout. In 2003 Symposium VLSI Technology Digest (pp. 133–135).
Park, J.-T., Colinge, J.-P., & Diaz, C. H. (2001). Pi-Gate SOI MOSFET. IEEE Electron Devices Letters, 22(8), 405–406.
Park, J.-T., & Colinge, J.-P. (2002). Multiple-gate SOI MOSFETs: Device design guidelines. IEEE Transactions on Electron Devices, 49(12), 2222–2228.
ATLAS (2003). V. 5.6.0. SILVACO© International, Santa Clara, CA.
Choi, Y.-K., King, T.-J., & Hu, Chenming. (2002). Spacer FinFET: Nanoscale double-gate CMOS technology for the terabit era. Solid-State Electronics, 46, 1595–1601.
Taur, Y., & Ning, T. (1998). Fundamentals of modern VLSI devices. Cambridge, UK: Cambridge University Press.
Breed, A. (2005). Design, simulation and analysis of the switching and RF performance of multi-gate silicon-on-insulator MOSFET device structures. Doctoral Dissertation, University of Cincinnati, Cincinnati.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Breed, A.A., Roenker, K.P. Comparison of the scaling characteristics of nanoscale SOI N-channel multiple-gate MOSFETs. Analog Integr Circ Sig Process 56, 135–141 (2008). https://doi.org/10.1007/s10470-007-9129-6
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-007-9129-6