Skip to main content
SpringerLink
Log in

Scaling prospect of optically differential reconfigurable gate array VLSIs

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

Dynamic reconfigurable devices present new computational paradigms because programmable devices’ activity and performance can be improved dramatically by increasing its reconfiguration frequency. Therefore, this paper presents designs of optically differential reconfigurable gate array (ODRGA) VLSIs using 0.18 μm and 0.35 μm CMOS process technologies. Although they are a type of programmable gate array, they can be reconfigured optically in nanoseconds. This paper also discusses future scaling prospects of ODRGA-VLSIs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. Altera Corporation, Altera devices, http://www.altera.com/products/devices/dev-index.jsp.

  2. Xilinx Inc., Silicon devices, http://www.xilinx.com/products/silicon_solutions/index.htm.

  3. Lattice Semiconductor Corporation, Key solutions/products, http://www.latticesemi.com.

  4. IPFlex Inc., Products, http://www.ipflex.com/en.

  5. Nakano, H., Shindo, T., Kazami, T., & Motomura, M. (2003) Development of dynamically reconfigurable processor LSI. NEC Technical Journal (Japan), 56(4), 99–102.

    Google Scholar 

  6. Dehon, A. (1996). Dynamically programmable gate arrays: A step toward increased computational density (pp. 47–54). Fourth Canadian Workshop on Field Programmable Devices.

  7. Scalera, S. M., & Vazquez, J. R. (1998). The design and implementation of a context switching FPGA (pp. 78–85). IEEE Symposium on FPGAs for Custom Computing Machines.

  8. Trimberger, S. et al. (1997). A time-multiplexed FPGA (pp. 22–28). FCCM.

  9. Jones, D., & Lewis, D. M.(1995). A time-multiplexed FPGA architecture for logic emulation. (pp. 495–498) Custom Integrated Circuits Conference.

  10. Mumbru, J., Panotopoulos, G., Psaltis, D., An, X., Mok, F., Ay, S., Barna, S., & Fossum, E. (2000). Optically programmable gate array. SPIE of Optics in Computing, 4089, 763–771.

    Google Scholar 

  11. Mumbru, J., Zhou, G., An, X., Liu, W., Panotopoulos, G., Mok, F., & Psaltis, D. (1999). Optical memory for computing and information processing. SPIE on Algorithms, Devices, and Systems for Optical Information Processing III, 3804, 14–24, 1999.

    Google Scholar 

  12. Mumbru, J., Zhou, G., Ay, S., An, X., Panotopoulos, G., Mok, F. & Psaltis, D. (1999). Optically Reconfigurable Processors. SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing, 74, 265–288.

    Google Scholar 

  13. Watanabe, M., & Kobayashi, F. (2002). An optically differential reconfigurable gate array and its power consumption estimation (pp. 197–202). IEEE International Conference on Field-Programmable Technology.

  14. Miyano, M., Watanabe, M., & Kobayashi, F. (2005). Rapid reconfiguration of an optically differential reconfigurable gate array with pulse lasers (pp. 287–288). IEEE International Conference on Field-Programmable Technology.

  15. Watanabe, M., & Kobayashi, F. (2004). An optically differential reconfigurable gate array using a 0.18 um CMOS process (pp. 281–284). IEEE International SOC Conference.

  16. Seto, D., & Watanabe, M. (2008). A dynamic optically reconfigurable gate array—perfect emulation. IEEE Journal of Quantum Electronics, 44(5), 493–500.

    Article  Google Scholar 

  17. Seto, D., & Watanabe, M. (2008). A dynamic optically reconfigurable gate array with a silver-halide holographic memory (pp. 511–514). IEEE Computer Society Annual Symposium on VLSI.

  18. Miyazaki, R., Watanabe, M., & Kobayashi, F. (2007). A multi-context holographic memory recording system for optically reconfigurable gate arrays. IEEE International Parallel & Distributed Processing Symposium, CD-ROM.

  19. Betz, V., & Rose, C. J. (1997). VPR: A new packing placement and routing tool for FPGA research. Seventh International Workshop on Field-Programmable Logic and Application.

Download references

Acknowledgments

This research is supported by the Ministry of Internal Affairs and Communications of Japan under the Strategic Information and Communications R&D Promotion Programme (SCOPE). The VLSI chip in this study was fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Rohm Co. Ltd. and Toppan Printing Co. Ltd.

Author information

Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Shizuoka University, 3-5-1 Johoku, Hamamatsu, Shizuoka, 432-8561, Japan

    Minoru Watanabe

  2. Sony LSI Design, Yokohama, Kanagawa, Japan

    Takenori Shiki

  3. Department of Systems Design and Informatics, Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka, 820-8502, Japan

    Fuminori Kobayashi

Authors
  1. Minoru Watanabe
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Takenori Shiki
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Fuminori Kobayashi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Minoru Watanabe.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Watanabe, M., Shiki, T. & Kobayashi, F. Scaling prospect of optically differential reconfigurable gate array VLSIs. Analog Integr Circ Sig Process 60, 137–143 (2009). https://doi.org/10.1007/s10470-008-9210-9

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-008-9210-9

Keywords

Search

Navigation