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An efficient power reduction technique for CMOS flash analog-to-digital converters

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Abstract

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm2 without I/O pads.

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References

  1. Choi, M., & Abidi, A. A. (2001). A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS. IEEE Journal of Solid-State Circuits, 36(12), 1847–1858. doi:10.1109/4.972135.

    Article  Google Scholar 

  2. Scholtens, P. C. S., & Vertregt, M. (2002). A 6-b 1.6-Gsample/s flash ADC in 0.18 μm CMOS using averaging termination. IEEE Journal of Solid-State Circuits, 37(12), 1599–1609. doi:10.1109/JSSC.2002.804334.

    Article  Google Scholar 

  3. Uyttenhove, K., & Steyaert, M. S. J. (2003). A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25 μm CMOS. IEEE Journal of Solid-State Circuits, 38(7), 1115–1122. doi:10.1109/JSSC.2003.813244.

    Article  Google Scholar 

  4. Terada, J., Matsuya, Y., Morisawa, F., & Kado, Y. (2000). 8-mW, 1-V, 100-MSPS, 6-bit A/D converter using a transconductance latched comparator. In: IEEE Asia Pacific conference on ASIC (pp. 53–56).

  5. Kim, S., & Song, M. (2001). An 8-bit 200MSPS CMOS A/D converter for analog interface module of TFT-LCD driver. In: IEEE international symposium on circuits and systems (pp. 528–531).

  6. Hotta, M. & Matsuura, T. (2006). Key technologies for miniaturization and power reduction of analog-to-digital converters for video use. In: IEICE transactions on electronics (Vol. E89-C, No. 6, pp. 664–672).

  7. Srinivas, V., Pavan, S., Lachhwani, A., & Sasidhar, N. (2006). A distortion compensating flash analog-to-digital conversion technique. IEEE Journal of Solid-State Circuits, 41(9), 1959–1969. doi:10.1109/JSSC.2006.880601.

    Article  Google Scholar 

  8. Scholtens, P. C. S., Smola, D., & Vertragt, M. (2005). Systematic power reduction and performance analysis of mismatch limited ADC designs. In: International symposium on low power electronics and design (pp. 78–83).

  9. Yoo, J., Lee, D., Choi, K., & Kim, J. (2002). A power and resolution adaptive flash analog-to-digital converter. In: International symposium on low power electronics and design (pp. 233–236).

  10. Tangel, A., & Choi, K. (2004). The CMOS inverter as a comparator in ADC designs. Analog Integrated Circuits and Signal Processing, 39(2), 147–155. doi:10.1023/B:ALOG.0000024062.35941.23.

    Article  Google Scholar 

  11. Tsai, C. C., Hong, K. W., Hwang, Y. S., Lee, W. T., & Lee, T. Y. (2004). New power saving design method for CMOS flash ADC. In: IEEE international midwest symposium on circuits and systems (pp. III-371–III-374).

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Acknowledgments

The authors would like to thank the reviewers for their valuable suggestions. The authors would also like to thank the Chip Implementation Center of Taiwan for the technical supporting and IC implementation. This work was supported by the National Science Council of Taiwan under Grant NSC 96-2221-E-027-130.

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Authors and Affiliations

  1. Department of Electronic Engineering, National Taipei University of Technology, Taipei, 106, Taiwan, ROC

    Yuh-Shyan Hwang, Po-Hsiang Huang, Bo-Han Hwang & Jiann-Jong Chen

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  1. Yuh-Shyan Hwang
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  2. Po-Hsiang Huang
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  3. Bo-Han Hwang
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  4. Jiann-Jong Chen
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Correspondence to Yuh-Shyan Hwang.

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Hwang, YS., Huang, PH., Hwang, BH. et al. An efficient power reduction technique for CMOS flash analog-to-digital converters. Analog Integr Circ Sig Process 61, 271–278 (2009). https://doi.org/10.1007/s10470-009-9309-7

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  • DOI: https://doi.org/10.1007/s10470-009-9309-7

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