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An improved low offset latch comparator for high-speed ADCs

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Abstract

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.

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Authors and Affiliations

  1. University of Tabriz, Tabriz, 51664, Iran

    Khosrov Dabbagh Sadeghipour

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  1. Khosrov Dabbagh Sadeghipour
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Correspondence to Khosrov Dabbagh Sadeghipour.

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Sadeghipour, K.D. An improved low offset latch comparator for high-speed ADCs. Analog Integr Circ Sig Process 66, 205–212 (2011). https://doi.org/10.1007/s10470-010-9509-1

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  • DOI: https://doi.org/10.1007/s10470-010-9509-1

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