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A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

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Abstract

This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and supply boosted (SB) circuits including level shifter, comparator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-Vt MOSFETs. A 10-bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 μm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are +0.8 and −0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/conversion-step. Proposed supply boosting technique improves input common mode range of both SB comparator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process.

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  1. Electrical and Computer Engineering, University of Idaho, Moscow, ID, USA

    Suat U. Ay

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Ay, S.U. A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS. Analog Integr Circ Sig Process 66, 213–221 (2011). https://doi.org/10.1007/s10470-010-9515-3

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  • DOI: https://doi.org/10.1007/s10470-010-9515-3

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