Skip to main content
Log in

A 16 bit 20 kHz bandwidth discrete-time ΣΔ modulator with VCO-based quantizer

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper the design of a 3rd-order 16 bit 20 kHz-bandwidth discrete-time ΣΔ modulator with voltage-controlled oscillator (VCO)-based quantizer is presented. This design is motivated by the trends towards die size and power consumption reduction together with performance robustness. In this direction, the flash converter embedded in a multi-bit ΣΔM is here replaced by a VCO and digital counter, resulting in a compact fully-digital quantizer implementation. This solution would greatly exploit the technology scaling. Moreover in the proposed feed-forward architecture all feed-forward paths are summed within the last integrator of the ΣΔ loop filter, thereby eliminating the need for an analog summation amplifier at the quantizer input The presented 3rd-order ΣΔM features 110 dB-SNR, 104 dB-SNDR (i.e. 16 bit-ENOB).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18

Similar content being viewed by others

References

  1. Iwata, A. (1999). The architecture of delta sigma analog-to-digital converters using a VCO as a multi bit quantizer. IEEE Transactions on Circuits Systems II, Analog and Digital Signal Processing, 46(8), 941–945.

    Article  Google Scholar 

  2. Miller, M. (2004). Multi-bit continuous time delta sigma ADC. US Patent 6,700,520. 2 Mar 2004.

  3. Straayer, M. Z., & Perrott, M. H. (2008). A 12-bit, 10-MHz bandwidth, continuous-time ∑Δ ADC with a 5-bit, 950-MS/s VCO-based quantizer. IEEE Journal of Solid-State Circuits, 43(4), 805–814.

    Article  Google Scholar 

  4. Schreier, R., & Temes, G. C. (2005). Understanding delta-sigma data converters. New York: IEEE Press.

    Google Scholar 

  5. San, H., Konagaya, H., Xu, F., Motozawa, A., Kobayashi, H., Ando, K., Yoshida, H., & Murayama, C. (2007). Second-order ΣΔAD modulator with novell feedforward architecture. Proc. 50th IEEE International Midwest Symposium on Circuits and System (MWSCAS 2007), Aug 2007, Montreal, Canada (pp. 148–151).

  6. Brigati, S., Francesconi, F., Malcovati, P., Tonietto, D., Baschirotto, A., & Maloberti, F. (1999). Modeling sigma-delta modulator non-idealities in SIMULINK. Proceedings of ISCAS99 (Vol. 2, pp. 384–387).

  7. Farat, M. A., Farag, F. A., & Elsimary, H. A. Only digital technology analog-to-digital converter circuit. Micro-NanoMechatronics and Human Science. 2003 IEEE International Symposium.

Download references

Acknowledgments

This project is partially funded by the Regione Puglia Explorative Project “Research and development of new sensors based on Samarium sulphide strain gauge”.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to M. De Blasi.

Rights and permissions

Reprints and permissions

About this article

Cite this article

De Blasi, M., Delizia, P., D’Amico, S. et al. A 16 bit 20 kHz bandwidth discrete-time ΣΔ modulator with VCO-based quantizer. Analog Integr Circ Sig Process 72, 521–529 (2012). https://doi.org/10.1007/s10470-011-9664-z

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-011-9664-z

Keywords

Navigation