1 Introduction

Nowadays, new generation communication systems are imposing two challenges in designing the analog-to-digital converters (ADCs). One challenge is increase of input signal frequency because of entering in several MHz bandwidth applications and the other is the high resolution ADCs, while the size of transistors and the circuit supply voltage are becoming smaller [1]. The design of an ADC oriented to ADSL application becomes a difficult task with technology scaling. Technology scaling, which is the most challenging factor in nano-scale processes, makes some issues on design of high performance op-amps, which are one of the crucial analog building blocks in the switch-capacitor (SC)-circuits ADCs. It decreases intrinsic gain (lower output resistance), voltage headroom and SNR while it increases device leakage, nonlinearity and mismatch [2, 3]. The most important problem is decreasing the device gain. It causes that, the precision in the feedback circuits is dramatically reduced, because in the traditional SC circuits a high gain op-amp determines the accuracy of the charge transfer. A method for achieving higher gain without reducing voltage swing is to cascade several gain stages, but it leads to the stability problem. Furthermore, high gain op-amp can be realized by cascoding transistors, but voltage headroom will be reduced. With decreasing the signal amplitude a larger capacitance and also more power consumption is needed to maintain the same SNR [4]. Different solutions have been introduced to deal with the power issue such as the time-to-digital converter (TDC) [5], incomplete settling [6] and switched op-amps [7]. Recently, a comparator-based switched-capacitor (CBSC) technique was reported in [8, 9] to replace the op-amp with comparator and current sources, which has the same operation like as op-amp-based architecture. In CBSC technique, a comparator and switched current sources are used to sense the virtual ground condition, instead of forcing it with an op-amp. One of the issues, which conventional architecture [8] suffers from it, is overshoot at the end of the coarse phase which decreases the speed and accuracy. The implementation of the SC overshoot correction circuit helps us to increase the speed (fastest settling) and decrease power consumption. In this paper design of high resolution and bandwidth sigma–delta modulator, which uses CBSC-based integrators and an op-amp-based IIR filter in its architecture, is investigated. The effectiveness of this hybrid architecture is justified through simulation using HSPICE in a 0.18 μm CMOS process and compared with the state-of-the-art SDMs.

2 Modulator architecture

There are two architectures for designing a Sigma–Delta modulator: Single-loop high-order and MASH (Cascade) SDM. In this article, we utilize single-loop high-order architecture for implementation of the modulator. In SDMs with traditional architecture the OTA employed in integrator needs a large swing, and must have a large DC gain and slew rate (SR) in order to overcome against nonlinear effects. High OTA DC gain results in high power consumption of the modulator. To solve this problem, we use CBSC structure instead of OTA in integrators. Moreover for decreasing the integrator swing, we applied a structure sigma–delta known as low-distortion [10], which uses feed-forward paths to decrease the integrator swing. This low-distortion modulator, illustrated in Fig. 1, just employs one digital to analog convertor (DAC) in main feedback path. In this structure, that uses feed-forward paths, the integrators in the modulator loop process only the quantization noise and prevent generation of large Swing. The single-loop high order.

Fig. 1
figure 1

Low-distortion sigma–delta modulator architecture

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SDMs may become unstable on large inputs; therefore in high-order structures we use the multi-bit quantizer. This causes settling in integrator to be relaxed more and decreases instability conditions. The proposed architecture is applied to a 5th-order single-loop SDM, with combination of CBSC-based integrators and Op-amp-based IIR filter. Figure 2 shows the modulator structure in which we used a 2nd-order IIR filter block instead of two integrators. The transfer function of the filter is represented in Eq. 1.

$$ H_{\text{IIR}} = \frac{{b_{1} z^{ - 1} + b_{2} z^{ - 2} }}{{1 - c_{1} z^{ - 1} - c_{2} z^{ - 2} }}. $$
(1)
Fig. 2
figure 2

The proposed 5th-order sigma–delta modulator architecture

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This method provides attractive results [11]; first the modulator architecture has less complexity in comparison with traditional structures. Second, the relation between in-band zeroes and noise transfer function (NTF) of SDM is simpler. In this manner, modulator coefficients spread is decreased and finally modulator sensitivity with respect to coefficient mismatching is reduced. The NTF has IIR structure with reverse chebyshev pole and zero. NTF for a 5th-order modulator with OSR = 8 is expressed as follows:

$$ {\text{NTF}}\left| {_{{{\text{OSR}} = 8}} } \right.(z) = \frac{{(z - 1)(z^{2} - 1.875z + 1)(z^{2} - 1.955z + 1)}}{{z^{5} - 1.2z^{4} + 1.119z^{3} - 0.495z^{2} + 0.276z^{1} - 0.0331}} $$
(2)

With some simple calculation, we can achieve coefficients values, which are presented in Fig. 2.

3 Design of key building blocks

3.1 CBSC gain stage

Figure 3 shows the complete CBSC-based integrator, along with its timing diagram. In φ1 phase, the input is sampled by the input capacitors (C S1 and C S2). The charge transfer phase φ2 is divided into four following sub-phases: (a) preset phase for preset switches (P rst), (b) coarse transfer phase (E1), (c) fine transfer phase (E2) and (d) settling phase (S = P rst + E1 + E2). After sampling, the outputs (Vop and Von) are preset to V REFP and V REFN. Preset phase (P rst) sets the output nodes to preset levels away from the common voltage level (V CM). After preset phase, coarse charge transfer phase is started. Ia current source charges the positive half circuit and discharges the negative half circuit simultaneously. As a result, input nodes of the comparator (V c and V d) are charged in opposite directions to cross each other to make the first decision as seen in Fig. 3(b). However, there is overshoot in the output due to the delay in the comparator and ramp rate (V ovp). Overshoot in the coarse phase is one of the most important limiting factors on the performance of the CBSC circuits. To reduce the primary overshoot at the end of the coarse phase, an SC overshoot correction circuit is introduced which shown in Fig. 3(a). For instance, at the end of the coarse phase, the amount of the primary overshoot is subtracted from V c and is stored in C ocp. This leads to the reduction of overshoot voltage, which has been produced in the coarse phase for saving power. After correction, the output voltage at the end of the coarse phase is defined as below:

$$ V_{\text{o}} = V_{\text{IN}} - D {\cdot} V_{\text{REF}} + \frac{{2I_{\text{a}}{\cdot} t_{\text{d1}} }}{{C_{\text{T}} }} - \Updelta V_{\text{OV}} $$
(3)
Fig. 3
figure 3

a CBSC-based integrator b timing diagram

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where Ia is the coarse current, D is the digital code determined by the quantizer and logics, C T is the total loading capacitance at the output of the gain stage and t d1 is the delay of the comparator for a coarse ramp input. The term ΔV ov is correcting factor, which decreases the overshoot voltage produced at the end of coarse phase (E1). To achieve more accurate output, the fine transfer phase is used. During this phase, fine current sources (Ib) are turned on to reduce the overshoot voltage and also achieve to the second detection as seen Fig. 3(b). The voltage comparator [12], is depicted in Fig. 4, consists of three stages: an input pre-amplifier (M1–M7), a decision stage (M8–M12) and an output buffer (M13–M17). The input stage (low-gain, high-bandwidth amplifier) converts the input voltages to currents level needed to drive the decision stage. The decision stage is a bistable cross-coupled circuit which switches from one state to another in accordance with the magnitude of the input currents. The positive feedback speeds up the switching. The output stage is used to convert the output voltage of the decision circuit into the digital logic signal. To reduce static power consumption, the comparator is controlled by signal S. When signal S is active (S = 1) V bias is connected to the circuit and the comparator is in the operation mode. If S is not active, (S = 0) path between V bias and circuit is disconnected and the comparator turns off. For coarse current sources which generate a large amount of current we used cascade current sources to achieve high output resistance for increasing the accuracy and linearity. A PMOS current source was used for the pull-up current, and a NMOS current source was used for the pull-down current during the coarse charge transfer phase. Also the effective open-loop gain A o of a CBSC circuit [8] is modeled as:

$$ A_{\text{O}} = \frac{{C_{\text{T}} \cdot R_{\text{O}} }}{{\alpha \cdot t_{d} }} $$
(4)
Fig. 4
figure 4

Threshold-detection comparator

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where C T is the total capacitance at the output of each stage, R o is the finite output resistance of the current source, t d is the delay of the threshold-detection comparator, and α denotes the feedback factor. For enhancing the accuracy in the fine current source [13] the controlling switch is connected to the drain. As a result when E2 is active (E2 = 1), it makes a cascade combination. So we have good accuracy in accordance with Eq. 4. During the transfer phase (φ2), a switched-capacitor common-mode feedback (CMFB) is used to control the pull down coarse current source. The CMFB circuit and current sources are shown in Fig. 5.

Fig. 5
figure 5

Current sources with CMFB circuit

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3.2 IIR filter

2nd-order IIR filter block is implemented as illustrated in Fig. 6(a). Because of low output swing of 2nd-order filter, 1st part can be made with single OTA that has the same accuracy and performance of 2nd-order filter with two OTAs [14] as depicted in Fig. 6(b). The p-path part of Fig. 6(b) is realized by capacitor C h1, which samples output in φ1 and transfers the relative charge to the capacitor C I3 in φ2. The q-path part achieves by delayed-sampling at feedback paths with two sampling capacitors (C h2). The mismatching between q-path capacitors causes to limit the attenuation of the quantization noise. Because of placing the IIR filter block in back-end stages, the error is shaped by previous stages, and with 0.4 percent capacitance mismatch, the SNDR remains above 85 dB. The second part of Fig. 6(a) can be combined with the last integrator of the modulator in order to perform the implementation of IIR filter block by means of single OTA. As shown in Fig. 7, a 2-stage folded-cascade class A OTA is employed to implement the IIR filter block [15]. In this structure, in addition to C s compensation capacitor, the C a capacitor is employed to keep circuit poles further away from zero frequency in order to attain higher rate and bandwidth with respect to conventional structures.

Fig. 6
figure 6

a The segregated diagram of 2nd-order IIR filter transfer function b 1st part implementation of IIR filter

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Fig. 7
figure 7

The OTA structure used in 2nd-order IIR filter

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3.3 Other parts of SDM

Figure 8 shows the switched capacitor implementation of SDM. As shown in Fig. 8, a passive adder at the input of quantizer is utilized for adding the feed-forward paths of the modulator [16]. This method does not need extra OTA, but causes the adder gain to be less than one. For alleviating this problem, we must use the scaling technique of reference voltage at quantizer input. After preparing the quantizer output that has 33 quantization levels, it is fed back to a DAC and the DAC output is subtracted from the input signal of the modulator. Because of DAC nonlinearity effects, we used a linearization algorithm called Data-Weighted Algorithm (DWA), in front of the DAC.

Fig. 8
figure 8

Fifth-order switched-capacitor delta–sigma modulator

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4 Simulation results

In this section, results obtained from system level simulation (MATLAB) and circuit level simulation using Hspice in 0.18 μm CMOS process are compared. Figure 9 shows the output power spectrum density (PSD) of the CBSC-based modulator with input signal amplitude -4 dBFS and input frequency f in = 109.375 kHz. Sampling frequency and Oversampling ratio are f s = 32MS/s and OSR = 8, which yields a signal bandwidth (BW) of 2 MHz. This spectrum, which computed via a 4096-FFT point, confirms the performance of this technique through comparison with conventional op-amp-based modulators as shown in Fig. 10. With a noise bandwidth (NBW) of 3.6e−4 Hz [17], the maximum values for the SNDR are 101 dB in the SIMULINK, 91.2 dB for the op-amp-based SDM and 85 dB for the CBSC-based SDM. Figure 11 shows the simulated SNDR versus the input signal amplitudes normalized by reference voltage (V ref). The dynamic range (DR) of CBSC-based modulator is 86.5 dB, which shows good agreement to the modulator simulated in MATLAB. The simulated power consumption is 18.75 mW from 1.8 V power supply, which obtains a figure of merit of 1.6e−3. Table 1 shows the performance comparison of state-of-the-art SDMs.

Fig. 9
figure 9

Simulated output spectrum of CBSC-based SDM at the transistor level

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Fig. 10
figure 10

PSD comparison between the approaches

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Fig. 11
figure 11

SNDR versus normalized input signal amplitude of the modulators

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Table 1 Performance comparison
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5 Conclusions

This letter addresses a 5th-order high resolution and broadband delta–sigma modulator with hybrid utilization of op-amp and CBSC circuit for ADSL applications. High performance low-distortion SDM is obtained by combination of integrator and IIR filter, which has less feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. Furthermore, we have employed CBSC gain stage to implement integrators which shows efficient architecture can be achieved for this application. In comparison with similar ones, the power dissipation is lower because of using CBSC integrators and decreasing number of OTA in 2nd-IIR filter block. With OSR = 8, the peak of SNDR is 85-dB, the bandwidth is about 2 MHz and the power is 18.75 mW. Simulation results verify the usefulness in implementation and fabrication of the proposed architecture.