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Synthesis and comparison of low-power high-throughput architectures for SAD calculation

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Abstract

Video applications are increasingly present in consumer electronic devices which require low-power and low-energy consumption. Sum of Absolute Differences (SAD) is the most used distortion metric in video coding implementation and consumes a relative large area in the motion estimation hardware. This paper presents the standard-cells synthesis and a comprehensive analysis of various parallel hardware architectures alternatives for SAD calculation, focusing on different design constraints such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (namely an isoperformance target). Low-power techniques supported by commercial standard-cells tools are exercised in this design, such as clock gating, multi-threshold (VT) and a combination of slow and fast standard-cells. We achieved significant power reduction for the architectures with lower frequencies and higher parallelism, slow cells and mainly with only one pipeline stage.

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Authors and Affiliations

  1. Informatics Institute, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brazil

    Fábio Leandro Walter, Cláudio Machado Diniz & Sergio Bampi

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  1. Fábio Leandro Walter
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  2. Cláudio Machado Diniz
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  3. Sergio Bampi
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Correspondence to Cláudio Machado Diniz.

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Walter, F.L., Diniz, C.M. & Bampi, S. Synthesis and comparison of low-power high-throughput architectures for SAD calculation. Analog Integr Circ Sig Process 73, 873–884 (2012). https://doi.org/10.1007/s10470-012-9971-z

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  • DOI: https://doi.org/10.1007/s10470-012-9971-z

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