Abstract
This paper presents a low voltage continuous-time delta–sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 \({\upmu }\)W from a 800 mV power supply.
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References
Schreier, R., & Temes, G. (2004). Understanding delta sigma data converters. Hoboken, NJ: Wiley.
Radjen, D., Anderson, M., Sundström, L., & Andreani, P. (2014). A low-power 2nd-order CT delta–sigma modulator with a single operational amplifier. Analog Integrated Circuits and Signal Processing, 80(3), 387–397.
Zanbaghi, R., Hanumolu, P. K., & Fiez, T. S. (2013). An 80-dB DR, 7.2-MHz bandwidth single opamp biquad based CT delta–sigma modulator dissipating 13.7-mW. IEEE Jounal of Solid-State Circuits, 48(2), 487–501.
Liu, L., Li, D., Ye, Y., & Wang, Z. (2011). A 92.4dB SNDR 24kHz delta--sigma modulator consuming 352 \(\mu\)W. In Proceedings of International Symposium on Low Power Electronics and Design, ISPLED’11 (pp. 351–356). Fukuoka, Japan, 1–3 August 2011.
Lee, C. C., & Flynn, M. P. (2011). A SAR-assisted two-stage pipeline ADC. IEEE Journnal of Solid-State Circuits, 46(4), 859–869.
Ranjbar, M., Mehrabi, A., Oliaei, O., & Carrez, F. (2010). A 3.1 mW continuous-time delta–sigma modulator with 6-bit successive approximation quantizer for WCDMA. IEEE Journal of Solid-State Circuits, 45(8), 1479–1491.
Tsai, H.-C., Lo, C.-L., Ho, C.-Y., & Lin, Y.-H. (2013). A 64-fJ/conv.-step continuous-time delta–sigma modulator in 40-nm CMOS using asynchronous SAR quantizer and digital delta–sigma truncator. IEEE Journal of Solid-State Circuits, 48(11), 1–12.
Cherry, J. A., & Snelgrove, W. M. (1999). Excess loop delay in continuous-time delta–sigma modulators. IEEE Transactions on Circuits and Systems II, 46, 376–389.
Benabes, P., Keramat, M., & Kielbasa, R. (1997). A methodology for designing continuous-time sigma-delta modulators. In European Design and Test Conference, EDTC (pp. 46–50), 17–20 March 1997.
Liu, C., Chang, S., Huang, G., & Lin, Y. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45(4), 731–740.
Schreier, R. (2000). The delta-sigma toolbox for MATLAB. www.mathworks.com/matlabcentral/fileexchange/.
Ranjbar, M., & Oliaei, O. (2011). A multibit dual-feedback CT delta–sigma modulator with lowpass signal transfer function. IEEE Transactions on Circuits and Systems I, 58(9), 2083–2095.
Ortmanns, M., & Gerfers, F. (2006). Continuous-time sigma–delta A/D conversion, fundamentals, performance limits and robust implementations. Berlin, Heidelberg: Springer.
Shoaei, O. (1996). Continuous-time delta-sigma A/D converters for high speed applications. Ph.D. Dissertation, Carleton University, Ottawa.
Pavan, S., Krishnapura, N., Pandarinathan, R., & Sankar, P. (2008). A power optimized continuous-time delta–sigma ADC for audio applications. IEEE Journal of Solid-State Circuits, 43(2), 351–360.
Matsukawa, K., Mitani, Y., Takayama, M., Obata, K., Dosho, S., & Matsuzawa, A. (2010). A fifth-order continuous-time delta–sigma modulator with single-opamp resonator. IEEE Journal of Solid-State Circuits, 45(4), 697–706.
Matsukawa, K., Obata, K., Mitani, Y., & Dosho, S. (2012). A 10 MHz 50 fJ/conv. continuous time delta--sigma modulator with high-order single opamp integrator using optimization-based design method. In Proceedings of the 2012 Symposium on VLSI Circuits (pp. 160–161). Honolulu, Hawaii, 13–15 Jun 2012.
Kauffman, J. G., Witte, P., Lehman, M., Becker, J., Manoli, Y., & Ortmanns, M. (2014). A 72 dB DR, CT delta–sigma modulator using digitally estimated, auxiliary DAC linearization achieving 88 fJ/conv-step in a 25 MHz BW. IEEE Journal of Solid-State Circuits, 49(2), 392–404.
Abdulaziz, M., Törmänen, M., & Sjöland, H. (2014). A compensation technique for two-stage differential OTAs. IEEE Transactions on Circuits and Systems II, 61(8), 594–598.
Chen, Y., Tsukanmoto, S., & Kuroda, T. (2009). A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS. In Proceedings of IEEE A-SSCC (pp. 145–148). Taipei, Taiwan, 16–18 Nov 2009.
van Elzakker, M., van Tuijl, E., Geraedts, P., & Schinkel, D. (2010). A 10-bit charge-redistribution ADC consuming 1.9 \(\mu\)W at 1 MS/s. IEEE Journal of Solid-State Circuits, 45(5), 1007–1015.
Harpe, P. J. A., Zhou, C., Bi, Y., van der Meijs, N. P., Wang, X., Philips, K., et al. (2011). A 26 \(\mu\)W 8 bit 10MS/s asynchronous SAR ADC for low energy radios. IEEE Journal of Solid-State Circuits, 46(7), 1585–1595.
Chen, S. M., & Brodersen, R. W. (2006). A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13\(\mu\)m CMOS. IEEE Journal of Solid-State Circuits, 41(12), 1669–2680.
Pavan, S., & Sankar, S. (2003). Power reduction in continuous-time delta--sigma modulators using the assisted opamp tecnique. In Proceedings of 29th IEEE ESSCIRC (pp. 198–201). Estoril, Portugal, 16–18 Sep 2003.
Weng, C., Lin, C., Chang, Y., & Lin, T. (2011). A 0.89-mW 1-MHz 62-dB SNDR continuous-time delta–sigma modulator with an asynchronous sequential quantizer and digital excess-loop-delay compensation. IEEE Transactions on Circuits and Systems I, 58(12), 867–871.
Luo, H., Cheung, R. C. C., Xiaopeng, L., & Tianlin, C. (2008). Design and measurement of a CT delta–sigma modulator with switched-capacitor switched-resistor feedback. IEEE Journal of Solid-State Circuits, 44(2), 473–483.
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Radjen, D., Anderson, M., Sundström, L. et al. A low-power 2nd-order CT delta–sigma modulator with an asynchronous SAR quantizer. Analog Integr Circ Sig Process 84, 409–420 (2015). https://doi.org/10.1007/s10470-015-0590-3
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DOI: https://doi.org/10.1007/s10470-015-0590-3