Abstract
A compensation technique for low-power three-stage operational transconductance amplifiers is presented in this paper. The compensation network is made up of passive components and entails only one Miller capacitor. Design equations describing the amplifier behavior for different capacitive load conditions are reported along with three design examples for different capacitive loads, namely, 1 nF, 100 and 10 pF. The amplifier exhibits a gain-bandwidth product equal to 2.48, 6.74 and 7.66 MHz in the three cases while dissipating only 150, 150 and 57.5 μW from 2.5 V, respectively. Simulation results are found in good agreement with theoretical analysis and show an improvement in both small-signal and large-signal amplifier performance over many previously reported solutions.
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Notes
\(tg\left( {\alpha + \beta } \right) = \frac{{{\text{tg}}\alpha + {\text{tg}}\beta }}{{1 - {\text{tg}}\alpha \cdot {\text{tg}}\beta }}\).
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Appendix
Appendix
The useful simplification from general complex and conjugate poles \(1 + a'_{2} s + a'_{3} s\) into two separate poles in (22) with (23) and (24) causes an error in the coefficient of s term, due to the term
Indeed, considering the relationship
into (25) we can write
which rearranged yields
Comparing (37) with the corresponding equation resulting from (19), we find the term \(g_{m1} R_{a}^{*} C_{o2}\) in the round bracket of the C m coefficient of (37). This is the term introduces an error that is negligible under the case of two separate poles (i.e., \(C_{L} /C_{o2} > g_{m2} g_{m3} R_{a}^{*2}\)).
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Di Cataldo, G., Grasso, A.D., Palumbo, G. et al. Improved single-miller passive compensation network for three-stage CMOS OTAs. Analog Integr Circ Sig Process 86, 417–427 (2016). https://doi.org/10.1007/s10470-016-0696-2
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DOI: https://doi.org/10.1007/s10470-016-0696-2