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Optimum design of a double-tail latch comparator on power, speed, offset and size

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Abstract

Transistor sizing is one of the most critical parts of comparator design which has a significant influence on comparator specifications. This paper presents an optimum design of a double-tail latch comparator based on transistor sizing with a great certainty to reach the best possible design due to using Hspice (as a software simulator) linked with a heuristic algorithm. To achieve a low-power, high-speed, low offset and, small size comparator, the multi-objective inclined planes optimization and Hspice were linked and several Pareto-fronts were obtained. As a result of analyzing the Pareto-fronts, power and total sizes of transistors have a tradeoff with delay and offset voltage. Meanwhile, the results comparison with a recent work shows the superiority of the present approach performance.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Birjand, Birjand, Iran

    Ehsan Yaqubi & Seyed Hamid Zahiri

Authors
  1. Ehsan Yaqubi
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  2. Seyed Hamid Zahiri
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Corresponding author

Correspondence to Ehsan Yaqubi.

Appendix

Appendix

See Table 5.

Table 6 Comparison between proposed comparator and other works
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Yaqubi, E., Zahiri, S.H. Optimum design of a double-tail latch comparator on power, speed, offset and size. Analog Integr Circ Sig Process 90, 309–319 (2017). https://doi.org/10.1007/s10470-016-0903-1

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  • DOI: https://doi.org/10.1007/s10470-016-0903-1

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