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A four-quadrant current multiplier/divider cell with four transistors

  • Mixed Signal Letter
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A Correction to this article was published on 09 March 2018

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Abstract

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.

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Change history

  • 09 March 2018

    The original version of this article unfortunately contained a mistake. The co-authors’ affiliation details were incorrect in the original publication of this article.

References

  1. Xu, J., Saavedra, C., & Guican, C. (2011). A 12 GHz bandwidth CMOS mixer with variable conversion gain capability. IEEE Microwave and Wireless Components Letters, 21(10), 565–567.

    Article  Google Scholar 

  2. Hsiao, S., & Chung-Yu, W. (1998). A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHZ RF downconversion mixer. IEEE Journal of Solid-State Circuits, 33(6), 859–869.

    Article  Google Scholar 

  3. Gilbert, B. (1968). A precise four-quadrant multiplier with subnanosecond response. IEEE Journal of Solid-State Circuits, 3(4), 365–373.

    Article  Google Scholar 

  4. Chaisayun, I., & Kobchai, D. (2003). A versatile CMOS analog multiplier. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86-A(5), 1225–1231.

    Google Scholar 

  5. Khachab, N., & Ismail, M. (1989). MOS multiplier/divider cell for analog VLSI. Electronics Letters, 25(23), 1550–1552.

    Article  Google Scholar 

  6. Khachab, N., & Ismail, M. (1991). A nonlinear CMOS analog cell for VLSI signal and information processing. IEEE Journal of Solid-State Circuits, 26(11), 1689–1699.

    Article  Google Scholar 

  7. Song, H., & Kim, C. (1990). An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers. IEEE Journal of Solid-State Circuits, 25(3), 841–847.

    Article  Google Scholar 

  8. Maundy, B., & Maini, M. (2003). A comparison of three multipliers based on the technique for low-voltage applications. IEEE Transactions on Circuits and Systems-I, 50(7), 937–940.

    Article  Google Scholar 

  9. Wong, S., Kalyanasundaram, N., & Salama, C. (1986). Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages. IEEE Journal of Solid-State Circuits, 21(6), 1120–1122.

    Article  Google Scholar 

  10. Li, Z., & Chen, C. (2006). Low-power low-noise CMOS analogue multiplier. IET Proceedings Circuits, Devices and Systems, 153(3), 261–266.

    Article  Google Scholar 

  11. Coban, A., & Allen, P. (1994). Low-voltage, four-quadrant, analogue CMOS multiplier. Electronics Letters, 30(13), 1044–1045.

    Article  Google Scholar 

  12. Han, B., & Sanchez-Sinencio, E. (1998). CMOS transconductance multipliers: A tutorial. IEEE Transactions on Circuits and Systems II, 45(12), 1150–1163.

    Google Scholar 

  13. Tanno, K., Ishizuka, O., & Tang, Z. (2000). Four-quadrant CMOS current-mode multiplier independent of device parameters. IEEE Transactions on Circuits and Systems II, 47(5), 473–477.

    Article  Google Scholar 

  14. Lopez-Martin, A., & Carlesona, A. (2001). Current-mode multiplier/divider circuits based on the MOS translinear principle. Analog Integrated Circuits and Signal Processing, 28(3), 265–278.

    Article  Google Scholar 

  15. Gilbert, B. (1974). A high-performance monolithic multiplier using active feedback. IEEE Journal of Solid State Circuits, 9(6), 364–373.

    Article  Google Scholar 

  16. Chible, H. (2015). Simulation of four-quadrant four transistors synapse analog multiplier. International Journal of Modeling and Simulation, 35(26), 49–56.

    Article  Google Scholar 

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Correspondence to Ahmed Elwakil.

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A correction to this article is available online at https://doi.org/10.1007/s10470-018-1157-x.

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Elwakil, A., Maundy, B., Elamien, M.B. et al. A four-quadrant current multiplier/divider cell with four transistors. Analog Integr Circ Sig Process 95, 173–179 (2018). https://doi.org/10.1007/s10470-018-1122-8

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  • DOI: https://doi.org/10.1007/s10470-018-1122-8

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