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A novel low offset low power CMOS dynamic comparator

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Abstract

This paper presents a novel fully dynamic double tail dynamic comparator that exhibits low offset voltage compared to the traditional dynamic comparators. This paper comprises a novel fully differential double tail high performance comparator suitable for low-voltage low-power applications. A fully differential double tail comparator has been intended to meet the necessity of low offset voltage with optimum power with relatively high speed. In this paper expression for the calculation of the offset voltage and delay of the proposed comparator are derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of dynamic comparator by analyzing the influence of each transistor pair individually. Transistor mismatch analysis is carried out for offset voltage to fully explore the trade-offs in the design of comparator. The results are validated by Monte Carlo simulations and corner analysis. It is shown that in proposed comparator offset voltage is significantly reduced with optimum power. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in 180 nm CMOS technology with ± 0.9 V supply. The Post-layout simulation results illustrates that a comparator designed with the proposed techniques is 45% faster, and 30% more power efficient and exhibits 91% low offset as compared with conventional comparator, which is the fastest among the conventional comparators.

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  1. EC Department, Institute of Technology, Nirma University, Ahmedabad, India

    Priyesh P. Gandhi & N. M. Devashrayee

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  1. Priyesh P. Gandhi
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  2. N. M. Devashrayee
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Correspondence to Priyesh P. Gandhi.

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Gandhi, P.P., Devashrayee, N.M. A novel low offset low power CMOS dynamic comparator. Analog Integr Circ Sig Process 96, 147–158 (2018). https://doi.org/10.1007/s10470-018-1166-9

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