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A low power, miniature temperature sensor with one-point calibrated accuracy of ± 0.25 °C from − 55 to 125 °C in 65 nm CMOS process

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Abstract

An ultra-low power and area, CMOS based temperature sensor with digital interface for military application (− 55 to 125 °C) is introduced. The sensor employs a proportional to absolute temperature current generator operating in sub-threshold region, and a novel signal-conditioning circuitry. A low power and area sigma-delta analog-to-digital converter (\(\varSigma \varDelta\)-ADC) is used for temperature to digital conversion. The \(\varSigma \varDelta\)-ADC is realized using second order \(\varSigma \varDelta\) modulator, where a self-biased, gain-boosted class-C inverter is shared between two stages for low power and low area, besides achieving a resolution of 12-bits. The overall sensor is realized in 65 nm CMOS standard process and its performance is validated using post-layout simulations, considering worst case. After one-trim, the sensor achieves an accuracy of \(\pm \,0.25\,^{\circ }\)C, while having a resolution of 0.18 °C and a resolution figure of merit of 0.0058 nJK2. The sensor operates at a power supply of 1-V, consuming power of 27.8 μW and an area of 0.0033 mm2 (excluding digital filter).

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Acknowledgements

This work has been performed using the resources of Mixed Signal Laboratory developed at Department of Electronics and Communication Engineering, National Institute of Technology Warangal, Telangana under Special Manpower Development Program for VLSI design and related software (SMDP-II) Project funded by Department of Information Technology, Ministry of Communication and Information Technology, Government of India.

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  1. Department of Electronics and Communication Engineering, National Institute of Technology Warangal, Warangal, Telangana, 506004, India

    Mudasir Bashir & Patri Sreehari Rao

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Correspondence to Mudasir Bashir.

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Bashir, M., Sreehari Rao, P. A low power, miniature temperature sensor with one-point calibrated accuracy of ± 0.25 °C from − 55 to 125 °C in 65 nm CMOS process. Analog Integr Circ Sig Process 99, 311–323 (2019). https://doi.org/10.1007/s10470-018-1278-2

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