Abstract
This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost constant and low ON-resistance (\(R_{ON}\)) over complete input signal range without using wide transistors, charge pumps, or both, at low supply voltages. The proposed switch was designed using standard 65 nm CMOS technology. The post-layout simulations have shown a signal to noise and distortion ratio (SNDR) of 87.81 dB, a spurious-free dynamic range (SFDR) of 90 dB and a total harmonic distortion (THD) of \(-91.5\,\hbox {dB}\) at a sampling frequency and supply voltage of 100 MHz and 0.8 V, respectively. In addition, the switch has shown a maximum variation of 1% in \(R_{ON}\) over input signal amplitude at different process corners and temperature, which is low compared to other sampling switches reported in the literature.
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Acknowledgements
This work is supported by early career research grant with Project Ref. ECR/2017/000931. This publication is also an outcome of the R & D work undertaken project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation.
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Tiwari, B., Bahubalindruni, P.G., Deb, S. et al. Robust linear sampling switch for low-voltage SAR ADCs. Analog Integr Circ Sig Process 103, 345–353 (2020). https://doi.org/10.1007/s10470-020-01641-w
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DOI: https://doi.org/10.1007/s10470-020-01641-w