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Impact of high-k spacer on device performance of a junctionless transistor

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Abstract

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I D ), ON-state to OFF-state current ratio (I ON /I OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G m R O ), output conductance (G D ), transconductance/drain current ratio (G m /I D ) and unity gain cut-off frequency (f T ). The effects of varying the spacer dielectric constant (k sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.

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Authors and Affiliations

  1. Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati-39, Assam, India

    Ratul Kumar Baruah & Roy P. Paily

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  1. Ratul Kumar Baruah
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  2. Roy P. Paily
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Correspondence to Ratul Kumar Baruah.

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Baruah, R.K., Paily, R.P. Impact of high-k spacer on device performance of a junctionless transistor. J Comput Electron 12, 14–19 (2013). https://doi.org/10.1007/s10825-012-0428-5

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