Skip to main content
SpringerLink
Log in

A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region

  • Published:
Journal of Computational Electronics Aims and scope Submit manuscript

Abstract

Breakdown voltage and specific on-resistance are two important parameters in lateral double diffused MOSFET (LDMOS) devices. In order to have a high breakdown voltage, the electric field profile should be uniform. In this paper a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage. Also, a triple P window is considered between these protruded oxides to have the balanced charge in the drift region that helps to have a higher breakdown voltage than a conventional LDMOS transistor. The simulation with two-dimensional ATLAS simulator shows that the proposed DP-LDMOS structure has a low specific on-resistance due to incorporating the protruded oxides in the drift region.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Vaid, R., Padha, N.: A novel trench gate floating islands power MOSFET (TG-FLIMOSFET) two dimensional simulation study. Microelectron. Eng. 88, 3316–3326 (2011)

    Article  Google Scholar 

  2. Choi, H., Shung, K.K.: Novel power MOSFET based expander for high frequency ultrasound systems. Ultrasonics 54, 121–130 (2014)

    Article  Google Scholar 

  3. Saremi, M., Saremi, M., Niazi, H., Goharrizi, A.Y.: Modeling of lightly doped drain and source grapheme nanoribbon field effect transistors. Superlattices Microstruct. 60, 67–72 (2013)

    Article  Google Scholar 

  4. Mehrad, M.: Omega shape channel LDMOS: a novel structure for high voltage applications. Physica E 75, 196–201 (2016)

    Article  Google Scholar 

  5. Arnold, E.: Silicon-on-insulator devices for high voltage and power IC applications. J. Electrochem. Soc. 141, 1983 (1994)

    Article  Google Scholar 

  6. Antognetti, P.: Power Integrated Circuits: Physics, Design and Applications. McGraw-Hill, New York (1986)

    Google Scholar 

  7. Cristoloveanu, S.: Silicon on insulator technologies and devices: from present to future. Solid State Electron. 45, 1403–1411 (2001)

    Article  Google Scholar 

  8. Colinge, J.P.: Silicon-on-Insulator Technology: Materials to VLSI, 3rd edn. Kluwer Academic Publishers, Boston (2004)

    Book  Google Scholar 

  9. Mehrad, M., Orouji, A.A.: A new nanoscale and high temperature field effect transistor: Bi level FinFET. Physica E 44, 654–658 (2011)

    Article  Google Scholar 

  10. Bawedin, M., Renaux, C., Flandre, D.: LDMOS in SOI technology with very-thin silicon film. Solid-State Electron. 48, 2263–2270 (2004)

    Article  Google Scholar 

  11. Mahabadi, S.E.J., Rajabi, S., Loiacono, J.: A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement. Superlattices Microstruct. 85, 872–879 (2015)

    Article  Google Scholar 

  12. Saremi, M., Ebrahimi, B., Kusha, A.A., Saremi, M.: Process variation study of ground plane SOI MOSFET. In: \(2^{{\rm nd}}\) Asia Symposium on Quality Electronic Design (ASQED), pp. 66–69 (2010)

  13. Saremi, M., Ebrahimi, B., Kusha, A.A., Mohammadi, S.: A partial-SOI LDMOS with triangular buried oxide for breakdown voltage improvement. Microelectron. Reliab. 51, 2069–2076 (2011)

    Article  Google Scholar 

  14. Mehrad, M., Orouji, A.A.: Injected charges in partial SOI LDMOSFETs: a new technique for improving the breakdown voltage. Superlattices Microstruct. 57, 77–84 (2013)

    Article  Google Scholar 

  15. Mehrad, M.: Controlling floating body effect in high temperatures: L-shape SiGe region in nano-scale MOSFET. Superlattices Microstruct. 85, 573–580 (2015)

    Article  Google Scholar 

  16. Mahabadi, S.E.J., Orouji, A.A., Keshavarzi, P., Rajabi, S., Moghadam, H.A., Haghighi, M.I.P.: A novel step buried oxide partial SOI LDMOSFET with triple drift layer. In: IEEE International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), India, pp. 174–177 (2011)

  17. Zareiee, M.: A novel high performance nano-scale MOSFET by inserting \({\rm Si}_{3}{\rm N}_{4}\) layer in the channel. Superlattices Microstruct. 88, 254–261 (2015)

  18. Orouji, A.A., Jamali Mahabadi, S.E., Keshavarzi, P.: A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement. Superlattices Microstruct. 50, 449–460 (2011)

    Article  Google Scholar 

  19. Mehrad, M.: Thin layer oxide in the drift region of laterally double-diffused metal oxide semiconductor on silicon-on-insulator: a novel device structure enabling reliable high temperature power transistors. Mater. Sci. Semicond. Process. 30, 599–604 (2015)

    Article  Google Scholar 

  20. Mehrad, M., Orouji, A.A.: New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using a SiGe zone in drift region. Curr. Appl. Phys. 12, 1340–1344 (2012)

    Article  Google Scholar 

  21. Mahabadi, S.E.J., Orouji, A.A., Keshavarzi, P., Moghadam, H.A.: A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage. Semicond. Sci. Technol. 26, 95005 (2011)

  22. Orouji, A.A., Mehrad, M.: Breakdown voltage improvement of LDMOSs by charge balancing: an inserted p-layer in trench oxide (IPT-LDMOS). Superlattices Microstruct. 51, 412–420 (2012)

    Article  Google Scholar 

  23. Atlas User’s Manual. Santa Clara, Silvaco International (2007)

  24. Cheng, X., Song, Z., Dong, Y., Yu, Y., Shen, D.: Patterned silicon-on-insulator technology for RF power LDMOSFET. Microelectron. Eng. 81, 150–155 (2005)

    Article  Google Scholar 

  25. Orouji, A.A., Mehrad, M.: The best control of parasitic BJT effect in SOI-LDMOS with SiGe window under channel. IEEE Trans. Electron Devices 59, 419–425 (2012)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. School of Engineering, Damghan University, Damghan, Iran

    Meysam Zareiee & Mahsa Mehrad

  2. Electrical and Computer Engineering Department, Semnan University, Semnan, Iran

    Ali A. Orouji

Authors
  1. Meysam Zareiee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ali A. Orouji
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mahsa Mehrad
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ali A. Orouji.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Zareiee, M., Orouji, A.A. & Mehrad, M. A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region. J Comput Electron 15, 611–618 (2016). https://doi.org/10.1007/s10825-015-0785-y

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10825-015-0785-y

Keywords

Search

Navigation