Abstract
This paper proposes a small chip area stochastic calibration for TDC linearity and input range, and analyzes it with FPGA. The proposed calibration estimates the absolute values of the delay of the buffers and the range of measurement statistically. The hardware implementation of the proposed calibration requires single counter to construct the histogram, so that the extra area for the proposed calibration is smaller. Because the implementation is fully digital, it is easily implemented on digital LSIs such as FPGA, micro-processor, and SoC. Experiments with Xilinx Virtex-5 LX FPGA ML501 reveal that both the periods of the external clock and the ring oscillator are preferred as short as possible under more than twice of the range of measurement of TDC when the oscillation period of the ring oscillator is wider than that of the external clock for fast convergence. The required time for the proposed calibration is 0.08 ms, and the required hardware resources LUTs and FFs for the implementation on FPGA are 24.1% and 22.2% of the conventional implementation, respectively.
Similar content being viewed by others
References
Chang YC, Huang SY, Tzeng CW, Yao J (2011) A fully cell-based design for timing measurement of memory. Proceedings International Test Conference (ITC’11) pp 1–10
Chujyo T, Hirabayashi D, Katoh K, Li C, Li E, Kobayashi Y, Wang J, Sato K, Kobayashi H (2014), Experimental verification of flash-type TDC with histogram method self-calibration. Proceedings IEE Electrical Circuit Research Meeting (ECT-14-006) pp 1–6
Hirabayashi D, Arakawa Y, Kawauchi S, Ishii M, Uemori S, Sato K, Kobayashi H, Niitsu K, Takai N (2012), Built-out self-test circuit for digital signal timing. Proceedings IEE Electrical Circuit Research Meeting (ECT-12-069) pp 1–6
Ito S, Nishimura S, Kobayashi H, Takai N , Vernier stochastic TDC architecture with self-calibration. Proceedings 4th international conference on Advanced Micro-Device Engineering (AMDE’12) pp 1–4 (2010)
Katoh K, Namba K, Ito H (2010), A low-area on-chip delay measurement system using embedded delay measurement circuit. Proceedings IEEE Asian Test Symposium (ATS’10) pp 343– 348
Kobayashi H, Aoki H, Katoh K, Li C (2014) Analog/mixed-signal circuit design in nano CMOS era. IEICE Electro Express 11(3):1–15
Komuro T, Jochen R, Shimizu K (2007) Kono M. IEICE Transac Electron J90-C(2):125–133
Kratyuk V, Hanumolu P, Ok K, Moon UK, Mayaram K (2009) A digital PLL with a stochastic time-to-digital converter. IEEE Transac Circ Sys I 56(8):1612–1621
Rivoir J (2006a) Fully-digital time-to-digital converter for ATE with autonomous calibration. Proceedings IEEE International Test Conference (ITC’06) pp 1–10
Rivoir J (2006b) Statistical linearity calibration of time-to-digital converters using a free-running ring oscillator. Proceedings IEEE Asian Test Symposium (ATS’06) pp 45–50
Tsai M C, Cheng CH, Yang CM (2008) An all-digital high-precision built-in delay time measurement circuit. Proceedings IEEE VLSI Test Symposium (VTS’08) pp 249–254
Verma S, Rategh HR, Lee TH (2003) A unified model for injection-locked frequency dividers. IEEE J of Solid-State Circ 38(6):1504–1512
Xilinx (2009) ML501 evaluation platform user guide. www.xilinx.com
Xilinx (2007) Virtex-5 CMT characterization report. www.xilinx.com
Xilinx (2012) Virtex-5 user guide. www.xilinx.com
Acknowledgements
This work is supported by the Semiconductor Technology Academic Research Center (STARC). The authors acknowledge Prof. Nobukazu Takai who gave us the variable suggestions.
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: J.-L. Huang
Rights and permissions
About this article
Cite this article
Katoh, K., Kobayashi, Y., Chujo, T. et al. A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J Electron Test 30, 653–663 (2014). https://doi.org/10.1007/s10836-014-5486-0
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-014-5486-0