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High Speed Error Tolerant Adder for Multimedia Applications

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Abstract

In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.

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References

  1. Adnan AN, Rizwan A, Damian D, Ronald FD (2015) Designing energy-efficient approximate adders using parallel genetic algorithms. Proc. SoutheastCon 1–7

  2. Andrew B, Seokhyeong K (2012) Accuracy-configurable adder for approximate arithmetic designs. Proc 49th ACM/EDAC/IEEE Design Autom Conf. doi: 10.1145/2228360.2228509

  3. Cong L, Jie H, Fabrizio L (2015) An analytical framework for evaluating the error characteristics of approximate adders. IEEE Trans Comput 64(5):1268–1281. doi:10.1109/TC.2014.2317180

    Article  MathSciNet  MATH  Google Scholar 

  4. Darjn E, Gerardo C, Davide DC, Ettore N, Nicola P, Antonio GM (2016) Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. Proc IEEE Int Symp Circuits Sys:1970–1973. doi:10.1109/ISCAS.2016.7538961

  5. Garg B, Dutt S, Sharma GK (2016) Bit-width-aware constant-delay run-time accuracy programmable adder for error-resilient applications. Microelectron J 50:1–7

    Article  Google Scholar 

  6. Haider AF, Almurib T, Nandhakumar, Fabrizio L (2016) Inexact Designs for Approximate Low Power Addition by Cell Replacement. Proc. Design, Automation & Test in Europe Conference & Exhibition. 660–665

  7. Honglan J, Jie H, Fabrizio L (2015) A comparative review and evaluation of approximate adders. Proc 25th Ed Great Lakes Symp VLSI 343–348. doi: 10.1145/2742060.2743760

  8. Ing CL, Yi MY, Cheng CL (2015) High-performance low-power carry speculative addition with variable latency. IEEE Trans Very Large Scale Integr (VLSI) Sys 23(9):1591–1603

    Article  Google Scholar 

  9. Irina A, Lau KT (2017) Approximate adder for low-power computations. Int J Electron Lett 5(2):158–165

    Article  Google Scholar 

  10. Jothin R, Vasanthanayaki C (2016) High performance significance approximation error tolerance adder for image processing applications. J Electron Test 32(3):377–383

    Article  Google Scholar 

  11. Junjun H, Weikang Q (2015) A New Approximate Adder with Low Relative Error and Correct Sign Calculation. Proc. Design, Automation & Test in Europe Conference & Exhibition. 1449–1454

  12. Kim S, Kim Y (2016) Energy-efficient hybrid adder design by using inexact lower bits adder. Proc IEEE Asia Pacific Conf Circuits Sys 355–357. doi: 10.1109/APCCAS.2016.7803974

  13. Li L, Hai Z (2014) On error modeling and analysis of approximate adders. Proc IEEE/ACM Int Conf Comput-Aided Des 511–518. doi: 10.1109/ICCAD.2014.7001399

  14. Manikantta R, Nithin K, Dheeraj S, Vasantha M H (2015) Low power, high speed error tolerant multiplier using approximate adders. Proc 19th Int Symp VLSI Des Test (VDAT) 1–6. doi: 10.1109/ISVDAT.2015.7208150

  15. Melvin A, Haiyang Z (2006) Error-tolerance and multi-media. Proc Int Conf Intell Inf Hiding Multimed Signal Proces. doi: 10.1109/IIH-MSP.2006.265055

  16. Mohapatra D, Chippa V, Raghunathan A, K. Roy (2011) Design of voltage-scalable meta-functions for approximate computing. Proc Des, Autom Test Eur Conf Exhib 1–6. doi: 10.1109/DATE.2011.5763154

  17. Muhammad S, Rehan H, Semeen R, Jörg H (2016) Cross-layer approximate computing: from logic to architectures. Proc 53rd Ann Des Autom Conf 1–6 doi: 10.1145/2897937.2905008

  18. Muhammad KA, Osman H, Muhammad S (2017) Statistical error analysis for low power approximate adders. Proc 54th Ann Des Autom Conf. doi: 10.1145/3061639.3062319

  19. Ning Z, Wang LG, Kiat SY (2009) An enhanced low-power high-speed Adder For Error-Tolerant application. Proc. 12th Int Symp Integr Circuits. 69–72

  20. Ning Z, Wang LG, Weija Z, Kiat SY, Zhi HK (2010) Design of low-Power High-Speed Truncation-Error-Tolerant Adder and its Application in digital signal processing. IEEE Trans Very Large Scale Integr Sys 18(8):1225–1229

    Article  Google Scholar 

  21. Ning Z, Wang LG, Gang W, Kiat SY (2010) Enhanced low-power high-speed adder for error-tolerant application. Proc. International SoC Design Conference (ISOCC). 323–327

  22. Omid A, Mehdi K, Ali AK, Pedram M (2016) RAP-CLA: a reconfigurable approximate carry look-ahead adder. IEEE Trans Circuits Sys II : Express Briefs 99:1–1. doi:10.1109/TCSII.2016.2633307

  23. Pawan S, Malathi P, Manish S (2015) Design of low power inexact 4:2 compressor using approximate adder. Proc Int Conf Comput, Commun Control 1–5. doi: 10.1109/IC4.2015.7375577

  24. Radek H, Vojtech M, Zdenek V (2016) Automatic Design of Approximate Circuits by means of multi-objective evolutionary algorithms. Proc Int Conf Des Technol Integr Sys Nanoscale Era 1–6. doi: 10.1109/DTIS.2016.7483885

  25. Ramkumar B, Harish M (2012) Low-power and area-efficient carry select adder. IEEE Trans Very Large Scale Integr Sys 20(2):371–375

    Article  Google Scholar 

  26. Rong Y, Ting W, Feng Y, Rakesh K, Qiang X (2013) On reconfiguration-oriented approximate adder design and its application. Proc. IEEE/ACM Int Conf Comput-Aided Des 48–54. doi: 10.1109/ICCAD.2013.6691096

  27. Rui Z, Weikang Q (2016) A general sign bit error correction scheme for approximate adders. Proc Int Great Lakes Symp VLSI 221–226. doi: 10.1145/2902961.2903012

  28. Sakthivel R, Harish M (2014) Energy efficient low area error tolerant adder with higher accuracy. J Circuits, Sys, Signal Process 33(8):2625–2641

    Article  Google Scholar 

  29. Sana M, Osman H, Rehan H, Muhammad S, Jörg H (2017) Probabilistic error modeling for approximate adders. IEEE Trans Comput 66(3):515–530

    Article  MathSciNet  MATH  Google Scholar 

  30. Sarabdeep S, Dilip K (2011) Design of Area and Power Efficient Modified Carry Select Adder. Int J Comput Appl 33(3):14–18

    Google Scholar 

  31. Statistical Error Analysis for Low Power Approximate Adders. http://save.seecs.nust.edu.pk/projects/SEALPAA

  32. Sunghyun K, Youngmin K (2016) Adaptive approximate adder (A3) to reduce error distance for image processor. Proc Int SoC Des Conf 295–296. doi: 10.1109/ISOCC.2016.7799794

  33. Sunil D, Sukumar N, Gaurav T (2016) A comparative survey of approximate adders. Proc 26th Int Conf Radioelektronika, doi: 10.1109/RADIOELEK.2016.7477392

  34. Vaibhav G, Debabrata M, Anand R, Kaushik R (2013) Low-power digital signal processing using approximate adders. IEEE Trans Comput-Aided Des Integr Circuits Sys 32(1):124–137

    Article  Google Scholar 

  35. Vincent C, Jeremy S, Christian E (2015) Energy-efficient digital design through inexact and approximate arithmetic circuits. Proc IEEE 13th Int New Circuits Sys Conf 1–4. doi: 10.1109/NEWCAS.2015.7182028

  36. Vincent C, Jeremy S, Christian E (2016) A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision. Proc 53nd ACM/EDAC/IEEE Des Autom Conf (DAC) 1–6. doi: 10.1145/2897937.2897964

  37. Vojtech M, Radek H, Zdenek V, Lukas S (2017) EvoApprox8b: library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. Des, Autom Test Eur Conf Exhib 258–261. doi: 10.23919/DATE.2017.7926993

  38. Weiqiang L, Linbin C, Chenghua W, Máire O, Fabrizio Lombardi (2014) Inexact floating-point adder for dynamic image processing. Proc IEEE 14th Int Conf Nanotechnol 239–243. doi: 10.1109/NANO.2014.6967953

  39. Xu Q, Mytkowicz T, Kim NS (2015) Approximate computing: a survey. IEEE Design & Test 33(1):8–22

    Article  Google Scholar 

  40. Yongtae K, Yong Z, Peng L (2013) An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems. Proc IEEE/ACM Int Conf Comput-Aided Des (ICCAD) 130–137. doi: 10.1109/ICCAD.2013.6691108

  41. Zhixi Y, Ajaypat J, Jinghang L, Jie H, Lombardi F (2013) Approximate XOR/XNOR-based adders for inexact computing. Proc IEEE Int Conf Nanotechnol 690–693. doi:10.1109/NANO.2013.6720793

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  1. Department of Electrical and Electronics Engineering, Coimbatore Institute of Technology, Coimbatore, India

    S. Geetha & P. Amritvalli

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  1. S. Geetha
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  2. P. Amritvalli
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Correspondence to S. Geetha.

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Responsible Editor: V. D. Agrawal

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Geetha, S., Amritvalli, P. High Speed Error Tolerant Adder for Multimedia Applications. J Electron Test 33, 675–688 (2017). https://doi.org/10.1007/s10836-017-5680-y

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